Method for detecting substrate crack, substrate, and detection circuit

• US 9,983,452 B2
• Filed: 07/15/2014
• Issued: 05/29/2018
• Est. Priority Date: 07/15/2014
• Status: Active Grant

• Current Assignee: Honor Device Company Limited
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Jia, Yanfeng, Tang, Lei, Xie, Pengfei
• Primary Examiner(s): Pizarro, Marcos D
• Assistant Examiner(s): TYNES JR., LAWRENCE C
• Application Number:
  US15/326,308
• Publication Number:
  US 20170199439A1
• Time in Patent Office: 1,414 Days
• Field of Search: 257 48
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G02F 1/1309 Repairing; Testing
• CPC Class Codes: G02F 1/133302 Rigid substrates, e.g. inorganic substrates
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136254 Checking; Testing
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A method for detecting a substrate crack, a substrate, and a detection circuit. A non-closed test line having an opening is peripherally disposed along an edge of a glass substrate of a TFT substrate. Whether an edge of the TFT substrate has a crack or chip can be determined by measuring whether the test line is on or off. In this way, a detection omission can be avoided, detection efficiency is improved, and after the TFT substrate is used to assemble a liquid crystal module or the liquid crystal module is used to assemble a complete device, whether the edge of the TFT substrate in the liquid crystal module has a crack or chip can also be detected.

Claims

1. An electronic terminal, comprising:

a liquid crystal display comprising a thin film transistor (TFT) substrate,

wherein the TFT substrate comprises a glass substrate,

wherein a non-closed test line having an opening is peripherally disposed on the glass substrate along an edge of the glass substrate,

wherein the opening is formed by two end points of the test line,

wherein one of the two end points is grounded,

wherein the opening is located in an interference fit flexible printed circuit board on glass (FOG) bonding region between a flexible printed circuit board and the glass substrate,

wherein the two end points of the opening are electrically connected to a first connector interface by using the flexible printed circuit board,

wherein the first connector interface is configured to electrically connect to a connector interface of a detection circuit, and

wherein the detection circuit is configured to measure whether the test line is on or off to determine whether an edge of the TFT substrate has a crack or chip.

2. The electronic terminal according to claim 1, wherein a conducting layer of the test line is manufactured as any conducting layer in a TFT substrate manufacturing process, and wherein the test line is manufactured together with a conductive pattern of the conducting layer in a patterning process for the conducting layer.

3. The electronic terminal according to claim 2, wherein the conducting layer is a gate metal layer, and wherein the conductive pattern of the conducting layer is a gate metal wire.

4. The electronic terminal according to claim 3, wherein a distance between the test line and the edge of the glass substrate is 150 micrometers (μ

m) to 200 μ

m.

5. The electronic terminal according to claim 2, wherein the conducting layer is a source drain metal layer, and wherein the conductive pattern of the conducting layer is a source drain metal wire.

6. The electronic terminal according to claim 5, wherein a distance between the test line and the edge of the glass substrate is 150 micrometers (μ

m) to 200 μ

m.

7. The electronic terminal according to claim 2, wherein the conducting layer is a transparent conducting thin film, and wherein the conductive pattern of the conducting layer is a pixel electrode.

8. The electronic terminal according to claim 7, wherein a distance between the test line and the edge of the glass substrate is 100 micrometers (μ

m).

9. The electronic terminal according to claim 1, further comprising a detection circuit, comprising:

an analog to digital converter interface;

a power supply;

a resistor;

a second connector interface; and

a test bed,

wherein the power supply is electrically connected to a first end of the resistor,

wherein a second end of the resistor is electrically connected to the second connector interface,

wherein a first end of the analog to digital converter interface is electrically connected to the second end of the resistor,

wherein a second end of the analog to digital converter interface is electrically connected to the test bed,

wherein a series circuit comprising the power supply, the resistor, and the TFT substrate is formed when a first connector interface in the TFT substrate is electrically connected to the second connector interface, and

wherein the test bed is configured to;

measure an electrical parameter at a connection point between the resistor and the second connector interface in the series circuit; and

determine whether an edge of the TFT substrate has the crack or chip according to the electrical parameter.