Providing per core voltage and frequency control

• US 9,983,661 B2
• Filed: 04/22/2016
• Issued: 05/29/2018
• Est. Priority Date: 09/23/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kumar, Pankaj, Nguyen, Hang T., Houghton, Christopher, Biermann, David A.
• Primary Examiner(s): Choudhury, Zahid
• Application Number:
  US15/135,670
• Publication Number:
  US 20160313785A1
• Time in Patent Office: 767 Days
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a plurality of cores formed on a semiconductor die, at least one of the plurality of cores including an instruction cache, a decoder to decode instructions, at least one execution unit to execute the decoded instructions, one or more register files, and at least one core-included cache memory, wherein the at least one of the plurality of cores comprises an out-of-order pipeline;

a shared cache memory;

an integrated memory controller;

at least one fully integrated voltage regulator formed on the semiconductor die; and

a power controller to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores, wherein the first core and the second core are to execute asymmetric workloads, the power controller to determine whether to update the voltage/frequency of the first core based at least in part on a workload, a thermal design power (TDP) budget and a temperature of the processor, and responsive to the determination to update the voltage/frequency provided to the first core, wherein the power controller is to send a control signal to the at least one fully integrated voltage regulator to cause the at least one fully integrated voltage regulator to provide the updated voltage to the first core.

2. The processor of claim 1, wherein the power controller is to control the voltage/frequency of the first core while remaining within a thermal budget.

3. The processor of claim 2, wherein the temperature comprises a temperature of the first core.

4. The processor of claim 1, wherein the plurality of cores, the shared cache memory and the fully integrated voltage regulator are formed on the semiconductor die comprising a single semiconductor die.

5. The processor of claim 1, wherein the power controller is to receive a performance state change request from an operating system (OS) for dynamic update of a voltage/frequency of one or more cores of the plurality of cores during OS operation, and determine whether to update the voltage/frequency based at least in part on the performance state change request.

6. The processor of claim 5, wherein the power controller is to increase provision of the voltage/frequency to the first core and to decrease provision of the voltage/frequency to the second core, based at least in part on the performance state change request.

7. The processor of claim 1, wherein the first core is to receive control information and a first voltage, and adjust the first voltage to a second voltage responsive to the control information.

8. The processor of claim 1, further comprising an uncore circuit comprising the power controller, the uncore circuit to operate at a first voltage and a first frequency for a first workload and to operate at a second voltage and a second frequency for a second workload.

9. The processor of claim 1, wherein the power controller includes an activity monitor to monitor micro-architectural activity, including instruction execution information, of the plurality of cores, and predict a usage of the first core in a future time period based on information from the activity monitor.

10. The processor of claim 1, wherein the at least one fully integrated voltage regulator comprises a plurality of fully integrated voltage regulators coupled to an external voltage regulator to provide an independent voltage to at least one of the plurality of cores.

11. A system comprising:

a processor;

a dynamic random access memory (DRAM) coupled to the processor;

a data storage, wherein the processor comprises;

a plurality of cores formed on a semiconductor die, at least one of the plurality of cores including a decoder to decode instructions, at least one execution unit to execute the decoded instructions, and at least one core-included cache memory, wherein the at least one of the plurality of cores comprises an out-of-order pipeline;

a shared cache memory;

an integrated memory controller;

at least one fully integrated voltage regulator formed on the semiconductor die; and

a power controller to control provision of a voltage to a first core of the plurality of cores independently of provision of a voltage to at least a second core of the plurality of cores, wherein the first core and the second core are to execute asymmetric workloads, the power controller to determine whether to update the voltage of the first core based at least in part on a workload, a thermal design power (TDP) budget and a temperature of the processor, and responsive to the determination to update the voltage provided to the first core, wherein the power controller is to send a control signal to the at least one fully integrated voltage regulator to cause the at least one fully integrated voltage regulator to provide the updated voltage to the first core.

12. The system of claim 11, comprising:

an audio output device coupled to the processor;

a graphics engine coupled to the processor; and

at least one communication device coupled to the processor.

13. The system of claim 11, wherein the processor further comprises an uncore circuit comprising the power controller, wherein the power controller is to cause a voltage of the uncore circuit to be reduced during execution of a first workload and cause at least one core to operate at a higher frequency during execution of the first workload, and cause the voltage of the uncore circuit to be increased during execution of a second workload and cause the at least one core to operate at a lower frequency during execution of the second workload.

14. The system of claim 11, wherein the power controller is to adjust a first set of the plurality of cores to execute at an increased voltage independently of a second set of the plurality of cores, so that the thermal design power (TDP) budget for the processor is maintained.

15. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

receiving, in a power controller of a processor, a request for a performance state change to at least one core of the processor, the processor comprising a plurality of cores formed on a semiconductor die, a shared cache memory, the power controller, a fully integrated voltage regulator formed on the semiconductor die and an integrated memory controller;

determining, in the power controller, whether to update a voltage provided to the at least one core based at least in part on a workload, a thermal design power (TDP) budget and a temperature of the processor; and

responsive to the determining, causing the voltage provided to the at least one core to be updated, including sending from the power controller a control signal to the fully integrated voltage regulator to cause the fully integrated voltage regulator to provide the updated voltage to the at least one core while at least one other core of the plurality of cores is provided with a second voltage, the second voltage different than the voltage provided to the at least one core and the updated voltage provided to the at least one core, the processor configured to enable independent performance states for at least some of the plurality of cores.

16. The non-transitory machine-readable medium of claim 15, wherein the method further comprises controlling the voltage provided to the at least one core while remaining within a thermal budget.

17. The non-transitory machine-readable medium of claim 15, wherein the method further comprises receiving the request for the performance state change from an operating system.

18. The non-transitory machine-readable medium of claim 17, wherein the method further comprises increasing provision of the voltage to the at least one core and decreasing provision of the second voltage to the at least one other core, based at least in part on the request for the performance state change.

19. The non-transitory machine-readable medium of claim 15, wherein the method further comprises:

monitoring micro-architectural activity, including instruction execution information, of the plurality of cores; and

predicting a usage of the at least one core in a future time period based the monitoring.