Information processing apparatus and data accessing method

• US 9,983,798 B2
• Filed: 06/06/2016
• Issued: 05/29/2018
• Est. Priority Date: 06/16/2015
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Konno, Hiroki
• Primary Examiner(s): Gu, Shawn X
• Application Number:
  US15/174,682
• Publication Number:
  US 20160370999A1
• Time in Patent Office: 722 Days
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Abstract

An information processing apparatus includes a first memory including a first portion and a second portion, the first portion including a plurality of regions, and a processor configured to read first data stored in a first region of the plurality of regions, move the first data stored in the first region to a second region, generate management data indicating that the first data is moved to the second region, store the management data in the second portion of the first memory, obtain information indicating a relation between the first data and location of the management data in the first memory, in response to a request to read the first data stored in the second region, access the management data based on the information, and read the first data stored in the second region.

Claims

1. An information processing apparatus comprising:

a memory including a first portion and a second portion, the first portion including a plurality of regions storing a plurality of data respectively; and

a processor coupled to the memory, the processor including a cache memory and configured to;

count a number of accessing to the plurality of data stored in the plurality of regions of the first portion of the memory respectively,

execute a rearrangement process of the plurality of data such that the plurality of data are stored in the plurality of regions of the memory respectively in descending order according to the number of accessing,

generate management data indicating that the plurality of data are stored in which region of the plurality of regions respectively after the rearrangement process,

store the management data in the second portion of the memory,

in response to a request to read first data of the plurality of data, access the management data stored in the second portion of the memory,

read, based on the management data, the first data stored in a first region of the plurality of regions, and

store, in the cache memory of the processor, the first data read from the first region of the plurality of regions and second data read from a second region of the plurality of regions next to the first region.

2. The information processing apparatus according to claim 1, wherein

the processor is further configured to:

delete, from the cache memory, data that is earliest stored in the cache memory, when a capacity of the cache memory is insufficient for storing new data.

3. The information processing apparatus according to claim 2, wherein the processor is further configured to, when the first data is stored in the cache memory, access the first data in the cache memory in response to the request to read the first data.

4. The information processing apparatus according to claim 1, wherein the processor is further configured to determine the first region for storing the first data based on an access frequency to the first data.

5. The information processing apparatus according to claim 1, wherein the processor is further configured to determine the first region every time a certain period of time has elapsed.

6. The information processing apparatus according to claim 5, wherein the processor is further configured to determine the first region, based on a priority determined for the first data, when the load in each of a plurality of times is within a certain range centered on a reference value that is determined for each of the plurality of times.

7. The information processing apparatus according to claim 1, wherein the processor is further configured to determine the first region, based on a number of times the first data is accessed.

8. The information processing apparatus according to claim 1, wherein:

the information processing apparatus includes a base station, and

the processor is further configured to determine the first region, based on a load on the information processing apparatus for communications with a mobile station.

9. The information processing apparatus according to claim 8, wherein the processor is further configured to determine the first region, based on a priority determined for the first data, in response to a change over time in the load.

10. A data accessing method using a memory and a processor coupled to the memory, the processor including a cache memory, the memory including a first portion and a second portion, the first portion including a plurality of regions storing a plurality of data respectively, the data accessing method comprising:

counting a number of accessing to the plurality of data stored in the plurality of regions of the first portion of the memory respectively;

executing a rearrangement process of the plurality of data such that the plurality of data are stored in the plurality of regions respectively in descending order according to the number of accessing;

generating management data indicating that the plurality of data are stored in which region of the plurality of regions respectively after the rearrangement process;

storing the management data in the second portion of the memory;

in response to a request to read first data of the plurality of data, accessing the management data stored in the second portion;

reading, based on the management data, the first data stored in a first region of the plurality of regions; and

storing, in the cache memory of the processor, the first data read from the first region of the plurality of regions and second data read from a second region of the plurality of regions next to the first region.

11. The data accessing method according to claim 10, further comprising:

deleting, from the cache memory, data that is earliest stored in the cache memory, when a capacity of the cache memory is insufficient for storing new data.

12. The data accessing method according to claim 11, further comprising:

when the first data is stored in the cache memory, accessing the first data in the cache memory in response to the request to read the first data stored.

13. The data accessing method according to claim 10, further comprising:

determining the first region for storing the first data based on an access frequency to the first data.

14. The data accessing method according to claim 10, further comprising:

determining the first region every time a certain period of time has elapsed.

15. The data accessing method according to claim 14, wherein the determining of the first region is executed based on a priority determined for the first data, when a load in each of a plurality of times is within a certain range centered on a reference value that is determined for each of the plurality of times.

16. The data accessing method according to claim 10, further comprising:

determining the first region, based on a number of times the first data is accessed.

17. The data accessing method according to claim 10, wherein the first memory and the processor are included in a base station, and the data accessing method further comprises determining the first region, based on a load on the base station for communications with a mobile station.

18. The data accessing method according to claim 17, wherein the determining of the first region is executed based on a priority determined for the first data in response to a change over time in the load.