Memory system with variable length page stripes including data protection information
First Claim
1. A non-volatile memory based solid state storage system comprising:
- a printed circuit board;
a plurality of non-volatile memory chips mounted to the printed circuit board, each non-volatile memory chip divided into planes, each plane divided into blocks, each block divided into pages, and each page including a plurality of non-volatile memory cells arranged to store a page of digital data, each non-volatile memory chip including a chip-level communications bus interface capable of receiving and sending digital data to be stored in, and retrieved from, non-volatile memory cells within the non-volatile memory chip; and
a system controller mounted to the printed circuit board, the system controller including a plurality of system communication bus interfaces, each system communication bus interface being coupled by a system communications bus to one or more chip-level communication bus interfaces such that the system controller can provide digital data to and retrieve digital data from memory cells within the one or more non-volatile memory chips, the system controller further including an external communications bus interface capable of receiving digital data to be stored within the storage system;
wherein the system controller is configured to store data received over the external communications bus in the plurality of non-volatile memory chips in the form of page stripes, each page stripe comprising a plurality of pages stored in the non-volatile memory chips, each of the plurality of pages being stored in a non-volatile memory chip that is different from, but in the same plane and block as, each of the non-volatile memory chips in which the other pages within the page stripe are stored, the plurality of pages making up each page stripe including;
a plurality of data pages, andat least one data protection page containing data protection information that may be used to reconstruct data stored in a data page within the page stripe that becomes corrupted or unavailable, the data protection information for a given page stripe being obtained by performing a bitwise logical operation on the information within the data pages for the given page stripe;
the page stripes stored by the system controller including;
a first page stripe stored within the plurality of non-volatile memory chips, the first page stripe having N data pages and one data protection page, where N is an integer greater than three; and
a second page stripe stored within the plurality of non-volatile memory chips, the second page stripe having M data pages and one data protection page, where M is an integer less than N, wherein each of the data pages within the second page stripe is stored within a non-volatile memory chip and a plane that also store data from a data page within the first page stripe and the data protection page for the first page stripe and the data protection page for the second page stripe can be located at any page location within the first page stripe and the second page stripe, respectively, including a first page location in the first and second data stripes.
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Accused Products
Abstract
Methods and apparatuses for enhanced protection of data stored in a non-volatile memory system involve a controller capable of adapting to the failure of one or more non-volatile memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different non-volatile memory device. The controller also detects failure of a non-volatile memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed non-volatile memory device.
96 Citations
20 Claims
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1. A non-volatile memory based solid state storage system comprising:
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a printed circuit board; a plurality of non-volatile memory chips mounted to the printed circuit board, each non-volatile memory chip divided into planes, each plane divided into blocks, each block divided into pages, and each page including a plurality of non-volatile memory cells arranged to store a page of digital data, each non-volatile memory chip including a chip-level communications bus interface capable of receiving and sending digital data to be stored in, and retrieved from, non-volatile memory cells within the non-volatile memory chip; and a system controller mounted to the printed circuit board, the system controller including a plurality of system communication bus interfaces, each system communication bus interface being coupled by a system communications bus to one or more chip-level communication bus interfaces such that the system controller can provide digital data to and retrieve digital data from memory cells within the one or more non-volatile memory chips, the system controller further including an external communications bus interface capable of receiving digital data to be stored within the storage system; wherein the system controller is configured to store data received over the external communications bus in the plurality of non-volatile memory chips in the form of page stripes, each page stripe comprising a plurality of pages stored in the non-volatile memory chips, each of the plurality of pages being stored in a non-volatile memory chip that is different from, but in the same plane and block as, each of the non-volatile memory chips in which the other pages within the page stripe are stored, the plurality of pages making up each page stripe including; a plurality of data pages, and at least one data protection page containing data protection information that may be used to reconstruct data stored in a data page within the page stripe that becomes corrupted or unavailable, the data protection information for a given page stripe being obtained by performing a bitwise logical operation on the information within the data pages for the given page stripe; the page stripes stored by the system controller including;
a first page stripe stored within the plurality of non-volatile memory chips, the first page stripe having N data pages and one data protection page, where N is an integer greater than three; and
a second page stripe stored within the plurality of non-volatile memory chips, the second page stripe having M data pages and one data protection page, where M is an integer less than N, wherein each of the data pages within the second page stripe is stored within a non-volatile memory chip and a plane that also store data from a data page within the first page stripe and the data protection page for the first page stripe and the data protection page for the second page stripe can be located at any page location within the first page stripe and the second page stripe, respectively, including a first page location in the first and second data stripes. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A board-mounted non-volatile-based memory storage system comprising:
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a printed circuit board; a plurality of non-volatile memory devices, each mounted to the printed circuit board and divided into planes, each plane divided into blocks, each block divided into pages, each page including a plurality of non-volatile memory cells arranged to store a page of data; a controller mounted to the printed circuit board; and a plurality of communications buses, each configured to allow the controller to write a data collection to one or more non-volatile memory devices; wherein the controller is configured to write data to the non-volatile memory devices in a striped fashion using data stripes, where each data stripe includes a group of data collections and an associated set of data protection information that can occupy any group location in the data stripe, including a first group location in the data stripe, such that; each data collection within a group of data collections is written into a non-volatile memory device that differs from, but in the same plane and block as; the non-volatile memory devices into which the other data collections within the group of data collections are written; and the non-volatile memory device to which the data protection information associated with the group of data collections is written; each data collection includes error correction code data generated from the data stored in the data collection; and each set of data protection information is generated by performing a bitwise exclusive-or (XOR) of the data within the data collections associated with the set of data protection information; wherein the controller is adapted to use the error correction code data within each data collection to identify an error within the data collection; wherein the controller further includes circuitry for using the set of data protection information to reconstruct the data for a data collection associated with the set of data protection information; and wherein the controller is configured such that the number of data collections within the group of data collections can vary. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A memory system comprising:
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a plurality of non-volatile memory chips, each of the plurality of non-volatile memory chips capable of storing a predefined number of bits of information and divided into planes, each plane divided into blocks, each block divided into pages, each page including a plurality of non-volatile memory cells arranged to store a page of data; a system controller coupled to the non-volatile memory chips, wherein the system controller writes information to the non-volatile memory chips using data stripes; a first data stripe stored in the plurality of non-volatile memory chips, the first data stripe including M data pages and a data protection page, where M is an integer greater than three and wherein information stored in the data protection page for the first data stripe was generated through the performance of a given operation on information stored within the M data pages of the first data stripe; and a second data stripe stored in the plurality of non-volatile memory chips, the second data stripe including N data pages and a data protection page, where N is an integer less than M, and wherein information stored in the data protection page for the second data stripe was generated from the performance of the given operation on information stored within the N data pages of the second data stripe; wherein each of the data pages within the second data stripe is stored within a non-volatile memory chip and plane that also store data from a data page within the first data stripe and the data protection page for the first page stripe and the data protection page for the second page stripe can be located at any page location within the first page stripe and the second page stripe, respectively, including a first page location in the first and second data stripes. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification