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Hierarchical visualization-based analysis of integrated circuits

  • US 9,984,195 B1
  • Filed: 03/15/2016
  • Issued: 05/29/2018
  • Est. Priority Date: 06/11/2010
  • Status: Active Grant
First Claim
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1. A method comprising:

  • formatting for display on a computer screen a layout of an integrated circuit design in a two-dimensional view, wherein the integrated circuit design is specified in a design database, the layout comprises multiple layers, and in the two-dimensional view, layers of the layout overlap when two or more layers cross each other on the screen;

    using a computer, allowing a user to identify a portion of the layout of the integrated circuit design using a pointer;

    using a computer, providing an option for the user to enable a three-dimensional view of the layout;

    after enabling the three-dimensional view option by the user, formatting for display on the screen at least the portion of the layout identified by the user in a three-dimensional view;

    allowing the user to specify a feature of the layout and allowing the user to request showing that feature using multiple colors in the three-dimensional view based on a property associated with the feature, wherein for a feature or portion of a feature havinga property value below a value V1, using a first color,the property value above the value V1, using a second color, and the first and second colors are different.

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