Tunable negative bitline write assist and boost attenuation circuit

• US 9,984,742 B2
• Filed: 04/13/2016
• Issued: 05/29/2018
• Est. Priority Date: 01/12/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chandra, Dinesh, Potladhurthi, Eswararao, Reddy, Dhani Reddy Sreenivasula, Rengarajan, Krishnan S.
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): Lozada, Alfredo Bermudez
• Application Number:
  US15/097,703
• Publication Number:
  US 20160232966A1
• Time in Patent Office: 776 Days
• Field of Search: 365156, 365189011, 36518916, 36518904, 3651892, 365154
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.

Claims

1. A device, comprising:

a memory array comprising a plurality of static random access memory (SRAM) cells;

a plurality of true bit lines each connected to a column of the memory array;

a plurality of complement bit lines each forming a differential pair with, and in a same column as, one of the plurality of true bit lines;

a write driver connected to each of the differential pair of bit lines in each of the plurality of SRAM cells of the memory array, the write driver comprising;

a negative boost node;

a discharge device coupled to ground and the negative boost node, the discharge device configured to receive a control signal and pull one of the plurality of true bit lines or one of the plurality of complement bit lines to ground in an active phase of a write cycle; and

a boost capacitor coupled to the negative boost node, the boost capacitor configured to boost the one of the plurality of true bit lines or the one of the plurality of complement bit lines below ground; and

a write assist attenuation circuit connected to the discharge device, the write assist attenuation circuit comprising a clamping device comprising an inverter, a first NFET, a second NFET, and a third NFET, each having a source-drain path connected to an output of the inverter which supplies the control signal to the source-drain paths of the first NFET, second NFET and third NFET, respectively, the clamping device being configured to modify the control signal as a function of supply voltage and process to attenuate an amount of the boost, and each of the first NFET, the second NFET, and the third NFET being connected to a first attenuation signal, a second attenuation signal, and a third attenuation signal, respectively,

wherein the source-drain paths of the first NFET, the second NFET and the third NFET are connected in parallel with one another between the supply voltage and the output of the inverter.

2. The device of claim 1, wherein a source of the first NFET is connected to the control signal, a drain of the first NFET is connected to an array supply voltage, and a gate of the first NFET is connected to the first attenuation signal.

3. The device of claim 2, wherein a source of the second NFET is connected to the control signal, a drain of the second NFET is connected to the array supply voltage, and a gate of the second NFET is connected to the second attenuation signal.

4. The device of claim 3, wherein a source of the third NFET is connected to the control signal, a drain of the third NFET is connected to the array supply voltage, and a gate of the third NFET is connected to the third attenuation signal.

5. The device of claim 4, wherein the first attenuation signal, the second attenuation signal, and the third attenuation signal are generated from a logic structure comprising a plurality of OR gates, and are configured to individually activate either the first NFET, the second NFET, or the third NFET such that only one of the first NFET, the second NFET, and the third NFET modify the control signal as a function of the supply voltage and the process to attenuate the amount of the boost.

6. The device of claim 5, wherein a width of the channel of each of the first NFET, the second NFET, and the third NFET is different such that each of the first NFET, the second NFET, and the third NFET modifies the control signal in a different manner.

7. The device of claim 6, wherein the width of the channel of the second NFET is less than the width of the channel of the first NFET, and the width of the channel of the first NFET is less than the width of the channel of the third NFET.

8. The device of claim 7, wherein the logic structure comprises an OR gate configured to generate a pulsed signal on the first attenuation signal, the second attenuation signal, and the third attenuation signal to allow for clamping of a signal until and during the boost and allow for the signal to proceed to ground after the boost.

9. A device, comprising:

a memory array comprising a plurality of memory cells;

a plurality of true bit lines each connected to a column of the memory array;

a plurality of complement bit lines each forming a differential pair with, and in a same column as, one of the plurality of true bit lines;

a write driver connected to each of the differential pair of bit lines in each of the plurality of memory cells of the memory array, the write driver comprising;

a negative boost node;

a discharge device coupled to ground and the negative boost node, the discharge device configured to receive a control signal and pull one of the plurality of true bit lines or one of the plurality of complement bit lines to ground; and

a boost capacitor coupled to the negative boost node, the boost capacitor configured to boost the one of the plurality of true bit lines or the one of the plurality of complement bit lines below ground; and

a write assist attenuation circuit connected to the discharge device, the write assist attenuation circuit comprising a clamping device comprising a first NFET, a PFET, and a second NFET,

a source of the first NFET being connected to a voltage source, a drain of the first NFET being connected to the discharge device, and a gate of the first NFET being connected to the control signal,

a source of the PFET being connected to an array supply voltage, a drain of the PFET being connected to the discharge device, and a gate of the PFET being connected to the control signal, and

a source of the second NFET being connected to the array supply voltage, and a drain of the second NFET being connected to the discharge device, such that the PFET and the second NFET are connected in parallel to one another between the array supply voltage and the discharge device, and a gate of the second NFET being connected to the control signal,

wherein a source-drain path of the second NFET is connected between the discharge device and a common node connecting source-drain paths of the first NFET and the PFET,

wherein the memory cells are static random access memory cells,

wherein the discharge device is comprised of an NFET configured to act like a diode, and

wherein the source-drain paths of the first NFET, the PFET and the second NFET are commonly connected to a gate of the NFET comprising the discharge device.

10. The device of claim 9, wherein the discharge device is configured to pull one of the plurality of true bit lines or one of the plurality of complement lines to ground in an active phase of a write cycle.

11. The device of claim 10, wherein the boost capacitor is coupled to a drain of the NFET comprising the discharge device.