Memory device and method for operating the same

• US 9,984,754 B2
• Filed: 03/12/2015
• Issued: 05/29/2018
• Est. Priority Date: 09/29/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Sakamoto, Wataru, Arai, Fumitaka, Kato, Tatsuya
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Techane, Muna A
• Application Number:
  US14/645,708
• Publication Number:
  US 20160093382A1
• Time in Patent Office: 1,174 Days
• Field of Search: 36518519
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

According to an embodiment, an operation method for a memory device which has a first memory element and a second memory element respectively provided on both sides of a semiconductor member includes applying a first potential on the second word line to write a second data to the second memory and applying a second potential on the first word line to write the first data to the first memory. The first potential increases by a first step voltage and the second potential increases by a second step voltage.

Claims

1. An operation method for a memory device including:

a first memory element provided on a first side of a semiconductor member, the first memory element having a first word line extending in a first direction and a first charge storage layer, the semiconductor member extending to a second direction, the first side of the semiconductor member being along the second direction;

a second memory element provided on a second side of the semiconductor member, the second memory element having a second word line extending in the first direction and a second charge storage layer, the second side being opposed on the first side with the semiconductor member in a third direction crossing the first direction and the second direction parallel to the substrate, the first memory element and the second memory element formed in common with the semiconductor member; and

a bit line extending in the third direction, an end of the first side being electrically connected to the bit line, an end of the second side being electrically connected to the bit line,

the operation method comprising;

when writing a first data to the first memory element,

applying a first potential on the second word line to write a second data to the second memory element, the first potential increasing by a first step voltage; and

applying a second potential on the first word line to write the first data to the first memory element, the second potential increasing by a second step voltage.

2. The method according to claim 1, wherein the first step voltage is larger than the second step voltage.

3. The method according to claim 2, wherein

the first potential is not less than 0 V, and

the applying the first potential increasing by the first step voltage includes:

after applying the first potential to write the second data to the second memory element;

applying a third potential on the second word line to read out the second data; and

applying a potential generated by adding the first step voltage to the first potential on the second word line.

4. The method according to claim 1, wherein the memory device further includes:

a third memory element provided on the first side of the semiconductor member, the third memory element having a third word line extending in the first direction and a third charge storage layer, the third memory element being provided adjacent to the first memory element in the second direction; and

the method further comprising;

applying the first potential on the third word line to write a third data to the third memory element before writing the first data to the first memory element.

5. The method according to claim 1, further comprising,

when writing a data to the second memory element,

applying the second potential on the second word line to write the data after writing the first data to the first memory element.

19. The device according to claim 1, wherein another end of the first side is connected to a source line and another end of the second side is connected to the source line.

6. A memory device comprising:

a substrate;

a first memory element provided on a first side of a semiconductor member, the first memory element having a first word line extending in a first direction and a first charge storage layer, the first charge storage layer being provided between the first word line and the semiconductor member, the semiconductor member extending to a second direction crossing the first direction, the first side of the semiconductor member being along the second direction;

a second memory element on a second side of the semiconductor member, the second memory element having a second word line extending in the first direction and a second charge storage layer, the charge storage layer being provided between the second word line and the semiconductor member, the second side being opposed on the first side in the third direction crossing the first direction and second direction parallel to the substrate with the semiconductor member, the first memory element and the second memory element formed in common with the semiconductor member;

a bit line extending in the third direction, an end of the first side being electrically connected to the bit line, an end of the second side being electrically connected to the bit line; and

a control unit configured to, when writing a first data to the first memory element,

apply a first potential on the second word line to write a second data to the second memory element, the first potential increasing by a first step voltage, and

apply a second potential on the first word line to write the first data to the first memory element, the second potential increasing by a second step voltage.

7. The device according to claim 6, wherein the first step voltage is larger than the second step voltage.

8. The device according to claim 7, wherein

the first potential is not less than 0 V, and

the control unit is configured to apply a third potential on the second word line to read out the second data and apply a potential generated by adding the first step voltage to the first potential on the second word line after the control unit applies the first potential to write the second data to the second memory element.

9. The device according to claim 6, further comprising:

a third memory element provided on the first side of the semiconductor member, the third memory element having a third word line extending in the first direction and a third charge storage layer, the third storage layer being provided between the third word line and the semiconductor member, the third memory element being provided adjacent to the first memory element in the second direction; and

the control unit being configured to apply the first potential on the third word line to write a third data to the third memory element before writing the first data to the first memory element.

10. The device according to claim 9, wherein, when writing a data to the second memory element, the control unit is configured to apply the second potential on the second word line to write the data after writing the first data to the first memory element.

11. A memory device comprising:

a first memory element provided on a first side of a semiconductor member, the first memory element including a first charge storage layer provide between a first electrode and the first side of the semiconductor member, the semiconductor member extending to a first direction, the first side of the semiconductor member being along the first direction;

a second memory element on a second side of the semiconductor member, the second memory element including a second charge storage layer provided between a second electrode and the second side of the semiconductor member, the second side being opposed on the first side with the semiconductor member, the first memory element and the second memory element formed in common with the semiconductor member;

a bit line extending in the second direction, an end of the first side being electrically connected to the bit line, an end of the second side being electrically connected to the bit line; and

a control unit configured to, when writing a first data to the first memory element,

apply a first potential on the second electrode to write a second data to the second memory element, the first potential increasing by a first step voltage,

before applying a second potential on the first electrode to write the first data to the first memory element, the second potential increasing by a second step voltage.

12. The device according to claim 11, wherein the first step voltage is larger than the second step voltage.

13. The device according to claim 12, wherein

the first potential is not less than 0 V, and

the control unit is configured to apply a third potential on the second electrode to read out the second data and apply a potential generated by adding the first step voltage to the first potential on the second electrode after the control unit applies the first potential to write the second data to the second memory element.

14. The device according to claim 11, further comprising:

a third memory element provided on the first side of the semiconductor member, the third memory element including a third charge storage layer provided between a third electrode and the first side of the semiconductor member, the third memory element being provided adjacent to the first memory element and provided in series with the first memory element,

the control unit being configured to apply the first potential on the third electrode to write a third data to the third memory element before writing the first data to the first memory element when writing a first data to the first memory element.

15. The device according to claim 14, wherein, when writing a data to the second memory element, the control unit is configured to apply the second potential on the second electrode to write the data after writing the first data to the first memory element.

16. The device according to claim 11, further comprising:

a first transistor provide on the first side of the semiconductor member and provided in series with the first memory element; and

a second transistor provided on the second side of the semiconductor member and provided in series with the second memory element,

the control unit being configured to turn on the first transistor and turn off the second transistor

when writing the data to the first memory element.

17. The device according to claim 11, wherein the first charge storage layer and the second charge storage layer include silicon.

18. The device according to claim 11, wherein the first electrode and the second electrode include silicon.