Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions

• US 9,984,894 B2
• Filed: 08/03/2011
• Issued: 05/29/2018
• Est. Priority Date: 08/03/2011
• Status: Active Grant

• Current Assignee: Auburn University, CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: Auburn University, CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Dhar, Sarit, Ryu, Sei-Hyung, Agarwal, Anant, Williams, John Robert
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US13/196,994
• Publication Number:
  US 20130034941A1
• Time in Patent Office: 2,491 Days
• Field of Search: 438197, 438770, 438775, 438923
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 21/3115 Doping the insulating layers
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

Methods of forming a semiconductor structure include providing an insulation layer on a semiconductor layer and diffusing cesium ions into the insulation layer from a cesium ion source outside the insulation layer. A MOSFET including an insulation layer treated with cesium ions may exhibit increased inversion layer mobility.

Claims

1. A method of forming a semiconductor structure, comprising:

providing an insulation layer on a semiconductor layer;

depositing a cesium ion source on the insulation layer; and

diffusing cesium ions from the cesium ion source into the insulation layer,

wherein diffusing the cesium ions from the cesium ion source into the insulation layer comprises annealing the insulation layer,

wherein depositing the cesium ion source on the insulation layer comprises boiling the insulation layer in a CsCl solution,

wherein providing the insulation layer on the semiconductor layer comprises forming and/or annealing the insulation layer in an environment containing nitrogen to nitridate the insulation layer and provide a nitridated insulation layer before depositing the cesium ion source on the insulation layer,

wherein diffusing the cesium ions from the cesium ion source into the insulation layer comprises diffusing cesium ions into the nitridated insulation layer, and

wherein, responsive to diffusing the cesium ions from the cesium ion source into the nitridated insulation layer, the semiconductor structure has a channel mobility of at least 40 cm²/V-s at an applied electric field of 3 MV/cm.

2. The method of claim 1, wherein diffusing the cesium ions into the insulation layer comprises diffusing the cesium ions to an interface between the insulation layer and the semiconductor layer.

3. The method of claim 1, wherein boiling the insulation layer in the CsCl solution comprises boiling the insulation layer in a 0.1 M to 1 M aqueous CsCl solution for 1 minute to 60 minutes at a temperature of about 90°

C. to about 100°

C.

4. The method of claim 1, wherein annealing the insulation layer comprises annealing the insulation layer at a temperature between about 700°

C. and about 1000°

C.

5. The method of claim 1, wherein providing the insulation layer comprises thermally oxidizing the semiconductor layer.

6. The method of claim 1, wherein providing the insulation layer comprises depositing the insulation layer on the semiconductor layer.

7. The method of claim 1, wherein the semiconductor layer comprises silicon carbide and the insulation layer comprises silicon dioxide.

8. The method of claim 1, wherein the semiconductor layer comprises polysilicon, amorphous silicon or gallium nitride.

9. The method of claim 1, wherein the nitridated insulation layer has a concentration of cesium ions of at least about 3×

10¹⁴ cm<sup>−

2</sup>.

10. A method of forming a field effect transistor device, comprising:

providing a semiconductor layer;

forming spaced apart source and drain regions in the semiconductor layer, the source and drain regions defining a channel region in the semiconductor layer;

providing an insulation layer on the semiconductor layer over the channel region;

depositing a cesium ion source on the insulation layer;

diffusing cesium ions from the cesium ion source into the insulation layer;

forming a gate electrode on the insulation layer; and

forming a contact on the source and drain regions,

wherein diffusing the cesium ions from the cesium ion source into the insulation layer comprises annealing the insulation layer,

wherein depositing the cesium ion source on the insulation layer comprises boiling the insulation layer in a CsCl solution,

wherein providing the insulation layer on the semiconductor layer over the channel region comprises forming and/or annealing the insulation layer in an environment containing nitrogen to nitridate the insulation layer and provide a nitridated insulation layer before depositing the cesium ion source on the insulation layer,

wherein diffusing the cesium ions from the cesium ion source into the insulation layer comprises diffusing cesium ions into the nitridated insulation layer, and

wherein, responsive to diffusing the cesium ions from the cesium ion source into the nitridated insulation layer, the channel region has a channel mobility of at least 40 cm²/V-s at an applied electric field of 3 MV/cm.

11. The method of claim 10, wherein diffusing the cesium ions from the cesium ion source into the insulation layer comprises diffusing the cesium ions to an interface between the insulation layer and the semiconductor layer.

12. The method of claim 10, wherein boiling the insulation layer in the CsCl solution comprises boiling the insulation layer in a 0.1 M aqueous CsCl solution for 10 minutes at a temperature of about 95°

C.

13. The method of claim 10, wherein annealing the insulation layer comprises annealing the insulation layer at a temperature between about 700°

C. and about 1000°

C.

14. The method of claim 10, wherein the semiconductor layer comprises silicon carbide and the insulation layer comprises silicon dioxide.

15. The method of claim 10, wherein the semiconductor layer comprises polysilicon, amorphous silicon or gallium nitride.

16. The method of claim 10, wherein the nitridated insulation layer has a concentration of cesium ions of at least about 3×

10¹⁴ cm<sup>−

2</sup>.