Method for making a microelectronic assembly having conductive elements

• US 9,984,901 B2
• Filed: 11/05/2015
• Issued: 05/29/2018
• Est. Priority Date: 12/23/2005
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Kang, Teck-Gyu, Mohammed, Ilyas, Chau, Ellis
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US14/933,225
• Publication Number:
  US 20160056058A1
• Time in Patent Office: 936 Days
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/4985 : Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method of making a microelectronic assembly can include molding a dielectric material around at least two conductive elements which project above a height of a substrate having a microelectronic element mounted thereon, so that remote surfaces of the conductive elements remain accessible and exposed within openings extending from an exterior surface of the molded dielectric material. The remote surfaces can be disposed at heights from said surface of said substrate which are lower or higher than a height of the exterior surface of the molded dielectric material from the substrate surface. The conductive elements can be arranged to simultaneously carry first and second different electric potentials: e.g., power, ground or signal potentials.

Claims

1. A method of making a microelectronic assembly comprising:

providing a microelectronic package including a substrate, a microelectronic element overlying said substrate, at least two conductive posts projecting from a first surface of said substrate, conductive pads, and terminals extending from a second surface of said substrate opposite said first surface, said at least two conductive posts each having a base adjacent said first surface of the substrate, a tip surface remote from said base and said first surface of said substrate, and an edge surface extending abruptly away from said tip;

compressing said at least two conductive posts so that each of said tips lie in a common plane and present at least substantially planar surfaces; and

molding an encapsulant material around said at least two conductive posts for supporting said microelectronic package and so that said remote, substantially planar surfaces of said at least two conductive posts remain accessible and exposed at an exterior surface of said molded encapsulant material,

wherein during said compressing said at least two conductive posts, said terminals are joined to said conductive pads.

2. The method as claimed in claim 1, wherein said terminals further comprise at least two second conductive posts projecting from a second surface of said substrate, said at least two second conductive posts having surfaces remote from said second surface of said substrate.

3. The method as claimed in claim 2, further comprising compressing said at least two second conductive posts so that said remote surfaces of said at least two second conductive posts lie in a common plane and present at least substantially planar surfaces.

4. The method as claimed in claim 1, wherein said substrate is flexible.

5. The method as claimed in claim 1, wherein said substrate comprises a dielectric material.

6. The method as claimed in claim 1, wherein said microelectronic element is electrically interconnected with said substrate.

7. The method as claimed in claim 1, wherein said microelectronic element is a semiconductor chip having a front face with contacts and a back face remote therefrom.

8. The method as claimed in claim 7, wherein the front face of said semiconductor chip faces said substrate.

9. The method as claimed in claim 7, wherein the front face of said semiconductor chip faces away from said substrate and the back face of said semiconductor chip faces said substrate.

10. The method as claimed in claim 1, wherein said microelectronic element is electrically interconnected with said substrate by conductive wiring.

11. The method as claimed in claim 1, further comprising a compliant layer disposed between said microelectronic element and said substrate.

12. The method as claimed in claim 1, wherein said substrate comprises a plurality of dielectric layers, and wherein a plurality of layers of conductive traces extend through said substrate.

13. The method as claimed in claim 1, further comprising making a second microelectronic package using the steps of claim 1, and stacking said second microelectronic package atop said first microelectronic package, wherein said first and second microelectronic packages are electrically interconnected together through said at least two conductive posts.

14. The method of claim 1, wherein said terminals further include conductive masses, and wherein said mold is heated to transform said conductive masses to an at least partially molten state for wetting said conducive masses to said conductive pads.

15. The method of claim 1, wherein said mold further includes recesses for receiving said conductive masses and said conductive masses are reflowed prior to joining said conductive masses with said conductive pads.

16. The method of claim 1, wherein during compressing said at least two conductive posts, said terminals are also compressed so that outer surfaces of said terminals lie in a common plane and present at least substantially planar surfaces.

17. A method of making a microelectronic assembly comprising:

providing a mold having an internal cavity;

placing a microelectronic package into said cavity of said mold, said microelectronic package including a substrate, a microelectronic element overlying said substrate, at least one conductive post projecting from a first surface of said substrate, said at least one conductive post having a surface remote from said first surface of said substrate, and conductive pads and terminals extending from a second surface of said substrate opposite said first surface;

utilizing said mold for compressing said at least one conductive post so that said remote surface lies in a plane and presents an at least substantially planar surface and so that said terminals are joined with said conductive pads; and

after the compressing and while said mold remains in contact with said remote surface of said at least one conductive post, introducing an encapsulant material into said cavity of said mold for encapsulating said microelectronic element and surrounding said at least one conductive post, wherein said mold remains in contact with said remote surface of said at least one conductive posts during the introducing said encapsulant material so that after said introducing an encapsulant material, said remote, substantially planar surface of said at least one conductive post remains accessible and exposed at an exterior surface of said encapsulant material and said terminals remain accessible and exposed at said second surface of said substrate.

18. The method as claimed in claim 17, wherein said substrate is a flexible dielectric substrate.

19. The method of claim 17, wherein surfaces of said terminals in contact with said mold also lie in a common plane and present at least substantially planar surfaces.