Systems and methods for aligning and coupling semiconductor structures

• US 9,984,943 B2
• Filed: 12/22/2016
• Issued: 05/29/2018
• Est. Priority Date: 05/16/2016
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Warner, Keith, D'Onofrio, Richard P., Yost, Donna-Ruth W.
• Primary Examiner(s): Sarkar, Asok K
• Application Number:
  US15/388,625
• Publication Number:
  US 20170330805A1
• Time in Patent Office: 523 Days
• Field of Search: None
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/75744 in the lower part of the bonding apparatus, e.g. in the apparatus chuck
• CPC Class Codes: H01L 2224/75745 in the upper part of the bonding apparatus, e.g. in the bonding head
• CPC Class Codes: H01L 2224/75753 Means for optical alignment, e.g. sensors
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80006 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/8013 using marks formed on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/821 Forming a build-up interconnect
• CPC Class Codes: H01L 2224/8313 using marks formed on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/9222 Sequential connecting processes
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout

Abstract

In a system for aligning at least two semiconductor structures for coupling, an alignment device includes a mounting structure having at least first and second opposing portions. The alignment device also includes a first mounting portion movably coupled to the first portion of the mounting structure, the first mounting portion configured to couple to a first surface of a first semiconductor structure. The alignment device additionally includes a second mounting portion movably coupled to the second portion of the mounting structure, the second mounting portion configured to couple to a second surface of a second semiconductor structure. The alignment device further includes one or more imaging devices disposed above at least one of the first and second mounting portions of the alignment device, the imaging devices configured to capture and/or or detect alignment marks in at least the first semiconductor structure. A corresponding method for aligning two or more semiconductor structures for coupling is also provided.

Claims

1. A method for aligning two or more semiconductor structures to be coupled, each of the semiconductor structures having first and second opposing surfaces, one or more layers of semiconductor material disposed between the first and second surfaces, and one or more alignment marks in at least one of the layers, the method comprising:

with a first spacing between the first and second semiconductor structures, capturing a first image of one or more alignment marks in each of the first and second semiconductor structures;

planarizing the first and second semiconductor structures;

changing the spacing between the first and second semiconductor structures from the first spacing to a second, different spacing;

at the second spacing, capturing a second image of one or more alignment marks in the at least one of the first and second semiconductor structures;

determining an alignment error value based upon a comparison of the first and second images of the alignment marks;

in response to the alignment error being greater than a predetermined threshold value, adjusting the alignment of the first and second semiconductor structures; and

in response to the alignment error being less than a predetermined threshold value, joining the first and second semiconductor structures.

2. The method of claim 1 wherein changing the spacing between the first and second semiconductor structures from the first spacing to a second different spacing comprises decreasing the spacing between the first and second semiconductor structures from the first spacing to the second spacing at which opposing surfaces of the first and second semiconductor structures are in physical proximity.

3. The method of claim 2, further comprising:

at the second spacing at which opposing surfaces of the first and second semiconductor structures are in physical contact, returning to the first spacing before bonding of the first and second semiconductor structures occurs.

4. The method of claim 1 wherein joining the first and second semiconductor structures comprises bonding the first and second semiconductor structures.

5. The method of claim 1 wherein capturing a first image of one or more alignment marks in each of the first and second semiconductor structures occurs at a first point in time and capturing a second image of one or more alignment marks in the at least one of the first and second semiconductor structures occurs at a second later point in time.

6. The method of claim 5 wherein determining the alignment error comprises comparing the captured one or more alignment marks at the first time and the captured one or more alignment marks at the second time.

7. The method of claim 1 wherein adjusting the alignment of the first and second semiconductor structures comprises changing the relative positions of the first and second semiconductor structures.

8. The method of claim 7 further comprising:

with a first spacing between the first and second alignment adjusted semiconductor structures, capturing a first image of one or more alignment marks in each of the first and second alignment adjusted semiconductor structures;

planarizing the first and second alignment adjusted semiconductor structures;

changing the spacing between the first and second alignment adjusted semiconductor structures from the first spacing to a second, different spacing;

at the second spacing, capturing a second image of one or more alignment marks in the at least one of the first and second alignment adjusted semiconductor structures; and

determining an alignment error value based upon a comparison of the first and second images of the alignment marks.

9. The method of claim 1 wherein changing the spacing between the first and second semiconductor structures from the first spacing to a second, different spacing comprises initiating contact between a first surface of the first semiconductor structure and a first surface of the second semiconductor structure at an initial point of contact.

10. The method of claim 1 wherein in response to the alignment error being less than an alignment error threshold, the method further comprises initiating contact between a first surface of the first semiconductor structure and a first surface of the second semiconductor structure at an initial point of contact.

11. The method of claim 10, wherein joining the first and second semiconductor structures comprises:

creating an initial bond between the first surface of the first semiconductor structure and the first surface of the second semiconductor structure at the initial point of contact; and

bonding the first surface of the first semiconductor structure and the first surface of the second semiconductor structure to form a bonded semiconductor structure.

12. The method of claim 11 further comprising:

annealing the bonded semiconductor structure at a predetermined temperature; and

forming electrical interconnections between the first and second semiconductor structures of the bonded semiconductor structure.

13. The method of claim 12 wherein forming electrical interconnections between the first and second semiconductor structures of the bonded semiconductor structure comprises:

forming electrical interconnections between the first and second semiconductor structures of the bonded semiconductor structure using complementary metal-oxide semiconductor (CMOS) lithography, plasma etching, and/or via filling processes.

14. The method of claim 1 wherein planarizing the first and second semiconductor structures comprises:

determining a best-fit plane of the second surface of the first one of the semiconductor structures;

determining a best-fit plane of the first surface of the second one of the semiconductor structures; and

comparing the best-fit plane of the second surface of the first one of the semiconductor structures with the best-fit plane of the first surface of the second one of the semiconductor structures to determine tilt and tip errors of the second surface of the first one of the semiconductor structures with respect to the first surface of the second one of the semiconductor structures.

15. The method of claim 14 further comprising:

positioning the second surface of the first one of the semiconductor structures substantially parallel with respect to the first surface of the second one of the semiconductor structures based upon the determined tilt and tip errors.