Integrated circuit containing DOEs of GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells

• US 9,984,944 B1
• Filed: 06/30/2016
• Issued: 05/29/2018
• Est. Priority Date: 12/16/2015
• Status: Expired due to Fees

• Current Assignee: PDF Solutions
• Original Assignee: PDF Solutions
• Inventors: Lam, Stephen, Ciplickas, Dennis, Brozek, Tomasz, Cheng, Jeremy, Comensoli, Simone, De, Indranil, Doong, Kelvin, Eisenmann, Hans, Fiscus, Timothy, Haigh, Jonathan, Hess, Christopher, Kibarian, John, Lee, Sherry, Liao, Marci, Lin, Sheng-Che, Matsuhashi, Hideki, Michaels, Kimon, O'Sullivan, Conor, Rauscher, Markus, Rovner, Vyacheslav, Strojwas, Andrzej, Strojwas, Marcin, Taylor, Carl, Vallishayee, Rakesh, Weiland, Larg, Yokoyama, Nobuharu
• Primary Examiner(s): Le, Son
• Application Number:
  US15/197,836
• Time in Patent Office: 698 Days
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2027/11866 Gate electrode terminals or contacts
• CPC Class Codes: H01L 2027/11875 Wiring region, routing
• CPC Class Codes: H01L 2027/11885 Two levels of metal
• CPC Class Codes: H01L 2027/11887 Three levels of metal
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/41725 : Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/45 : Ohmic electrodes

Abstract

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes, including GATECNT-tip-to-side-short and/or GATECNT-tip-to-side-leakage failure modes. Such wafers, chips, or dies may include Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, of at least two types, all targeted to the same failure mode.

Claims

1. An integrated circuit (IC), comprising at least:

a mix of logic cells and fill cells of different widths and uniform heights;

wherein the integrated circuit includes at least a first Design of Experiments (DOE), the first DOE comprising at least two gate contact (GATECNT)-tip-to-side-short-configured, non-contact electrical measurement (NCEM)-enabled fill cells, wherein each GATECNT-tip-to-side-short-configured, NCEM-enabled fill cell comprises at least;

first and second elongated conductive supply rails, formed in at least one metal layer, extending horizontally across the entire width of the cell, and configured for compatibility with corresponding supply rails contained in the logic cells;

a NCEM pad, formed in at least one conductive layer;

a plurality of at least four elongated, uniformly spaced gate (GATE) stripes, each extending in a parallel, longitudinal, vertical direction from a vertical position proximate to the first supply rail to a vertical position proximate to the second supply rail;

at least one tip-to-side test region, defined by first and second GATECNT features;

a first conductive pathway that electrically connects the first GATECNT feature to the NCEM pad; and

,

a second conductive pathway that electrically connects the second GATECNT feature to a permanently or virtually grounded structure;

wherein each of the GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells in the first DOE is configured to present a short circuit or excessive leakage between its first and second GATECNT features as abnormally high pad-to-ground conductance or abnormally low pad-to-ground resistance, detectable by voltage contrast (VC) inspection of the pad; and

,

wherein the GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells of the first DOE differ at least in terms of their respective probabilities of presenting a short circuit or excessive leakage failure at the pad.

2. An IC, as defined in claim 1, wherein the first DOE is contained within a contiguous standard cell region that includes both logic cells and NCEM-enabled fill cells.

3. An IC, as defined in claim 1, wherein the first DOE is contained within a contiguous fill cell only region.

4. An IC, as defined in claim 3, wherein the contiguous fill cell only region is placed between standard cell logic regions.

5. An IC, as defined in claim 1, wherein the NCEM pads of the first and second GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells each comprise a multi-conductor mesh pad.

6. An IC, as defined in claim 1, wherein the NCEM pads of the first and second GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells each comprise an enlarged first wiring layer (M1) feature.

7. An IC, as defined in claim 6, wherein the enlarged M1 feature is key-shaped.

8. An IC, as defined in claim 6, wherein the enlarged M1 feature is rectangular.

9. An IC, as defined in claim 6, wherein the enlarged M1 feature is J-shaped.

10. An IC, as defined in claim 1, further comprising at least one additional fill cell, selected from the list consisting of:

source/drain (AA)-tip-to-tip-short-configured, NCEM-enabled fill cells;

source/drain contact (AACNT)-tip-to-tip-short-configured, NCEM-enabled fill cells;

AACNT-AA-tip-to-tip-short-configured, NCEM-enabled fill cells;

AACNT-source/drain silicide (TS)-tip-to-tip-short-configured, NCEM-enabled fill cells;

TS-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATE-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATECNT-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-tip-to-tip-short-configured, NCEM-enabled fill cells;

via to interconnect stack (V0)-tip-to-tip-short-configured, NCEM-enabled fill cells;

first wiring layer (M1)-tip-to-tip-short-configured, NCEM-enabled fill cells;

M1-V0-tip-to-tip-short-configured, NCEM-enabled fill cells;

first interconnect via (V1)-M1-tip-to-tip-short-configured, NCEM-enabled fill cells;

V1-tip-to-tip-short-configured, NCEM-enabled fill cells;

second wiring layer (M2)-tip-to-tip-short-configured, NCEM-enabled fill cells;

M2-V1-tip-to-tip-short-configured, NCEM-enabled fill cells;

second interconnect via (V2)-M2-tip-to-tip-short-configured, NCEM-enabled fill cells;

third wiring layer (M3)-tip-to-tip-short-configured, NCEM-enabled fill cells;

V2-tip-to-tip-short-configured, NCEM-enabled fill cells;

M3-V2-tip-to-tip-short-configured, NCEM-enabled fill cells;

AA-tip-to-side-short-configured, NCEM-enabled fill cells;

AACNT-tip-to-side-short-configured, NCEM-enabled fill cells;

AACNT-AA-tip-to-side-short-configured, NCEM-enabled fill cells;

GATE-AA-tip-to-side-short-configured, NCEM-enabled fill cells;

TS-GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-tip-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-tip-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-TS-tip-to-side-short-configured, NCEM-enabled fill cells;

M1-tip-to-side-short-configured, NCEM-enabled fill cells;

V0-tip-to-side-short-configured, NCEM-enabled fill cells;

M1-V0-tip-to-side-short-configured, NCEM-enabled fill cells;

V1-M1-tip-to-side-short-configured, NCEM-enabled fill cells;

V1-tip-to-side-short-configured, NCEM-enabled fill cells;

M2-tip-to-side-short-configured, NCEM-enabled fill cells;

M2-V1-tip-to-side-short-configured, NCEM-enabled fill cells;

V2-M2-tip-to-side-short-configured, NCEM-enabled fill cells;

M3-tip-to-side-short-configured, NCEM-enabled fill cells;

V2-tip-to-side-short-configured, NCEM-enabled fill cells;

M3-V2-tip-to-side-short-configured, NCEM-enabled fill cells;

AA-side-to-side-short-configured, NCEM-enabled fill cells;

AACNT-side-to-side-short-configured, NCEM-enabled fill cells;

AACNT-AA-side-to-side-short-configured, NCEM-enabled fill cells;

AACNT-GATE-side-to-side-short-configured, NCEM-enabled fill cells;

GATE-side-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-side-to-side-short-configured, NCEM-enabled fill cells;

TS-GATE-side-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-side-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-side-to-side-short-configured, NCEM-enabled fill cells;

M1-side-to-side-short-configured, NCEM-enabled fill cells;

V0-side-to-side-short-configured, NCEM-enabled fill cells;

M1-V0-side-to-side-short-configured, NCEM-enabled fill cells;

V1-M1-side-to-side-short-configured, NCEM-enabled fill cells;

V1-side-to-side-short-configured, NCEM-enabled fill cells;

M2-side-to-side-short-configured, NCEM-enabled fill cells;

M2-V1-side-to-side-short-configured, NCEM-enabled fill cells;

V2-M2-side-to-side-short-configured, NCEM-enabled fill cells;

M3-side-to-side-short-configured, NCEM-enabled fill cells;

V2-side-to-side-short-configured, NCEM-enabled fill cells;

M3-V2-side-to-side-short-configured, NCEM-enabled fill cells;

AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

AACNT-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATE-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATE-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-GATE-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-GATECNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M1-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M1-GATECNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M1-V0-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V1-M1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V1-V0-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M2-M1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M2-V1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V2-V1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V2-M2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M3-M2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M3-V2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

AA-diagonal-short-configured, NCEM-enabled fill cells;

TS-diagonal-short-configured, NCEM-enabled fill cells;

AACNT-diagonal-short-configured, NCEM-enabled fill cells;

AACNT-AA-diagonal-short-configured, NCEM-enabled fill cells;

GATE-diagonal-short-configured, NCEM-enabled fill cells;

GATE-AACNT-diagonal-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-diagonal-short-configured, NCEM-enabled fill cells;

GATECNT-diagonal-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-diagonal-short-configured, NCEM-enabled fill cells;

M1-diagonal-short-configured, NCEM-enabled fill cells;

V0-diagonal-short-configured, NCEM-enabled fill cells;

M1-V0-diagonal-short-configured, NCEM-enabled fill cells;

V1-M1-diagonal-short-configured, NCEM-enabled fill cells;

V1-diagonal-short-configured, NCEM-enabled fill cells;

M2-diagonal-short-configured, NCEM-enabled fill cells;

M2-V1-diagonal-short-configured, NCEM-enabled fill cells;

M3-diagonal-short-configured, NCEM-enabled fill cells;

V2-M2-diagonal-short-configured, NCEM-enabled fill cells;

V2-diagonal-short-configured, NCEM-enabled fill cells;

M3-V2-diagonal-short-configured, NCEM-enabled fill cells;

AA-corner-short-configured, NCEM-enabled fill cells;

AACNT-corner-short-configured, NCEM-enabled fill cells;

AACNT-AA-corner-short-configured, NCEM-enabled fill cells;

GATE-corner-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-corner-short-configured, NCEM-enabled fill cells;

GATECNT-TS-corner-short-configured, NCEM-enabled fill cells;

GATECNT-corner-short-configured, NCEM-enabled fill cells;

GATECNT-AA-corner-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-corner-short-configured, NCEM-enabled fill cells;

M1-corner-short-configured, NCEM-enabled fill cells;

V0-corner-short-configured, NCEM-enabled fill cells;

M1-V0-corner-short-configured, NCEM-enabled fill cells;

V1-M1-corner-short-configured, NCEM-enabled fill cells;

V1-corner-short-configured, NCEM-enabled fill cells;

M2-corner-short-configured, NCEM-enabled fill cells;

M2-V1-corner-short-configured, NCEM-enabled fill cells;

M3-corner-short-configured, NCEM-enabled fill cells;

V2-M2-corner-short-configured, NCEM-enabled fill cells;

V2-corner-short-configured, NCEM-enabled fill cells;

M3-V2-corner-short-configured, NCEM-enabled fill cells;

GATE-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATE-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATE-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATECNT-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATECNT-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-GATE-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M1-GATECNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M1-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V1-V0-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M2-M1-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V2-V1-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M3-M2-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-GATECNT-via-chamfer-short-configured, NCEM-enabled fill cells;

V0-AACNT-via-chamfer-short-configured, NCEM-enabled fill cells;

V1-M1-via-chamfer-short-configured, NCEM-enabled fill cells;

V2-M2-via-chamfer-short-configured, NCEM-enabled fill cells;

V3-M3-via-chamfer-short-configured, NCEM-enabled fill cells;

V0-merged-via-short-configured, NCEM-enabled fill cells;

V1-merged-via-short-configured, NCEM-enabled fill cells;

V2-merged-via-short-configured, NCEM-enabled fill cells;

AA-snake-open-configured, NCEM-enabled fill cells;

TS-snake-open-configured, NCEM-enabled fill cells;

AACNT-snake-open-configured, NCEM-enabled fill cells;

GATE-snake-open-configured, NCEM-enabled fill cells;

GATECNT-snake-open-configured, NCEM-enabled fill cells;

V0-snake-open-configured, NCEM-enabled fill cells;

M1-snake-open-configured, NCEM-enabled fill cells;

M1-V0-AACNT-snake-open-configured, NCEM-enabled fill cells;

V1-snake-open-configured, NCEM-enabled fill cells;

M2-snake-open-configured, NCEM-enabled fill cells;

V2-snake-open-configured, NCEM-enabled fill cells;

M3-snake-open-configured, NCEM-enabled fill cells;

AA-stitch-open-configured, NCEM-enabled fill cells;

TS-stitch-open-configured, NCEM-enabled fill cells;

AACNT-stitch-open-configured, NCEM-enabled fill cells;

GATECNT-stitch-open-configured, NCEM-enabled fill cells;

V0-stitch-open-configured, NCEM-enabled fill cells;

M1-stitch-open-configured, NCEM-enabled fill cells;

V1-stitch-open-configured, NCEM-enabled fill cells;

M2-stitch-open-configured, NCEM-enabled fill cells;

V2-stitch-open-configured, NCEM-enabled fill cells;

M3-stitch-open-configured, NCEM-enabled fill cells;

AACNT-TS-via-open-configured, NCEM-enabled fill cells;

AACNT-AA-via-open-configured, NCEM-enabled fill cells;

TS-AA-via-open-configured, NCEM-enabled fill cells;

GATECNT-GATE-via-open-configured, NCEM-enabled fill cells;

GATECNT-AACNT-via-open-configured, NCEM-enabled fill cells;

GATECNT-AACNT-GATE-via-open-configured, NCEM-enabled fill cells;

V0-GATECNT-via-open-configured, NCEM-enabled fill cells;

V0-AA-via-open-configured, NCEM-enabled fill cells;

V0-TS-via-open-configured, NCEM-enabled fill cells;

V0-AACNT-via-open-configured, NCEM-enabled fill cells;

V0-GATE-via-open-configured, NCEM-enabled fill cells;

V0-via-open-configured, NCEM-enabled fill cells;

M1-V0-via-open-configured, NCEM-enabled fill cells;

V1-via-open-configured, NCEM-enabled fill cells;

V1-M1-via-open-configured, NCEM-enabled fill cells;

V1-M2-via-open-configured, NCEM-enabled fill cells;

M1-GATECNT-via-open-configured, NCEM-enabled fill cells;

M1-AANCT-via-open-configured, NCEM-enabled fill cells;

V2-M2-via-open-configured, NCEM-enabled fill cells;

V2-M3-via-open-configured, NCEM-enabled fill cells;

V3-via-open-configured, NCEM-enabled fill cells;

M4-V3-via-open-configured, NCEM-enabled fill cells;

M5-V4-via-open-configured, NCEM-enabled fill cells;

M1-metal-island-open-configured, NCEM-enabled fill cells;

M2-metal-island-open-configured, NCEM-enabled fill cells;

M3-metal-island-open-configured, NCEM-enabled fill cells;

V0-merged-via-open-configured, NCEM-enabled fill cells;

V0-AACNT-merged-via-open-configured, NCEM-enabled fill cells;

V0-GATECNT-merged-via-open-configured, NCEM-enabled fill cells;

V1-merged-via-open-configured, NCEM-enabled fill cells;

V2-merged-via-open-configured, NCEM-enabled fill cells;

V1-M1-merged-via-open-configured, NCEM-enabled fill cells; and

,

V2-M2-merged-via-open-configured, NCEM-enabled fill cells.

11. An IC, as defined in claim 1, wherein for each of the fill cells of the first DOE, the first conductive pathway comprises only a V0 feature.

12. An IC, as defined in claim 1, wherein for each of the fill cells of the first DOE, the first conductive pathway comprises GATE and GATECNT features.

13. An IC, as defined in claim 12, wherein for each of the fill cells of the first DOE, the first conductive pathway additionally comprises an AACNT feature.

14. An IC, as defined in claim 1, wherein for each of the fill cells of the first DOE, the second conductive pathway comprises GATE and GATECNT features.

15. An IC, as defined in claim 14, wherein for each of the fill cells of the first DOE, the second conductive pathway additionally comprises an AACNT feature.

16. An IC, as defined in claim 14, wherein for each of the fill cells of the first DOE, the second conductive pathway additionally comprises a V0 feature.

17. An IC, as defined in claim 1, wherein both of the at least two GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells of the first DOE include only a single NCEM pad.

18. An IC, as defined in claim 1, wherein at least one of the GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells of the first DOE includes multiple NCEM pads.

19. An IC, as defined in claim 1, wherein for each of the fill cells of the first DOE, at least some of the GATE stripes are broken, and at least some of the GATE stripes are unbroken.

20. An IC, as defined in claim 1, wherein the at least two GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells of the first DOE are both variants of the same cell.

21. An IC, as defined in claim 1, wherein the first DOE contains at least three GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells, all of which are variants of the same cell.