Integrated circuit and manufacturing method thereof

• US 9,985,031 B2
• Filed: 03/18/2016
• Issued: 05/29/2018
• Est. Priority Date: 01/21/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Che-Cheng, Lin, Chih-Han, Tseng, Horng-Huei
• Primary Examiner(s): KIELIN, ERIK J
• Application Number:
  US15/074,985
• Publication Number:
  US 20170213828A1
• Time in Patent Office: 802 Days
• Field of Search: None
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/3215 Doping the layers
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.

Claims

1. An integrated circuit comprising:

a substrate;

at least one n-type semiconductor device present on the substrate, wherein;

the n-type semiconductor device comprises a first semiconductor fin,

the n-type semiconductor device comprises a first gate structure having;

a first bottom surface overlying a first top surface of the first semiconductor fin;

a first sidewall overlying the first top surface; and

a second sidewall overlying the first top surface, and

the first bottom surface and the first sidewall intersect to form a first interior angle;

the first bottom surface and the second sidewall intersect to form a second interior angle; and

at least one p-type semiconductor device present on the substrate, wherein;

the p-type semiconductor device comprises a second semiconductor fin,

the p-type semiconductor device comprises a second gate structure having;

a second bottom surface overlying a second top surface of the second semiconductor fin;

a third sidewall overlying the second top surface; and

a fourth sidewall overlying the second top surface, and

the second bottom surface and the third sidewall intersect to form a third interior angle smaller than the first interior angle and the second interior angle,

the second bottom surface and the fourth sidewall intersect to form a fourth interior angle smaller than the first interior angle and the second interior angle,

a width of the second bottom surface is greater than a width of the first bottom surface, and

a second cross-sectional area of the second gate structure at a top of the second semiconductor fin is larger than a first cross-sectional area of the first gate structure at a top of the first semiconductor fin.

2. The integrated circuit of claim 1, wherein the first interior angle is an obtuse angle.

3. The integrated circuit of claim 1, wherein the first interior angle is a substantially right angle.

4. The integrated circuit of claim 1, wherein the second gate structure comprises:

a p-type work function layer having a third top surface facing away from the second top surface and a fifth sidewall overlying the second top surface, wherein;

the third top surface and the fifth sidewall intersect to form a fifth interior angle, and

the fifth interior angle is an acute angle.

5. The integrated circuit of claim 1, wherein the third interior angle is an acute angle.

6. The integrated circuit of claim 1, wherein the second gate structure consists of a first number of layers greater than one.

7. The integrated circuit of claim 6, wherein:

the first gate structure consists of a second number of layers greater than one, and

the first numbers of layers is greater than the second number of layers.

8. The integrated circuit of claim 1, wherein the n-type semiconductor device further comprises:

a gate dielectric having;

a third top surface overlying the first top surface and interfacing with the first bottom surface, and

a third bottom surface overlying the first top surface and interfacing with the first top surface.

9. The integrated circuit of claim 1, wherein:

the second gate structure comprises;

a first work function material layer forming a third interior angle equal to the second interior angle; and

a second work function material layer forming a fourth interior angle equal to the first interior angle.

10. The integrated circuit of claim 9, wherein the first work function material layer is in contact with a first dielectric layer underlying the second gate structure.

11. The integrated circuit of claim 10, wherein the first gate structure comprises the second work function material layer forming a fifth interior angle equal to the first interior angle.

12. The integrated circuit of claim 11, wherein the second work function material layer, of the first gate structure, is in contact with a second dielectric layer underlying the first gate structure.

13. An integrated circuit comprising:

a substrate;

at least one n-type semiconductor device present on the substrate, wherein;

the n-type semiconductor device comprises a first semiconductor fin,

the n-type semiconductor device comprises a first gate structure,

the first gate structure comprises a first top portion overlying a first top surface of the first semiconductor fin and a first bottom portion overlying the first top surface and present between the first top portion and the first top surface,

the first top portion has a first top width, and

the first bottom portion has a first bottom width; and

at least one p-type semiconductor device present on the substrate, wherein;

the p-type semiconductor device comprises a second semiconductor fin,

the p-type semiconductor device comprises a second gate structure,

the second gate structure comprises a second top portion overlying a second top surface of the second semiconductor fin and a second bottom portion overlying the second top surface and present between the second top portion and the second top surface,

the second top portion has a second top width,

the second bottom portion has a second bottom width, and

the first gate structure and the second gate structure substantially satisfy;

(Wb2-Wt2)>

(Wb1-Wt1), wherein Wb1 is the first bottom width, Wt1 is the first top width, Wb2 is the second bottom width, and Wt2 is the second top width resulting in a second cross-sectional area of the second gate structure at a top of the second semiconductor fin being larger than a first cross-sectional area of the first gate structure at a top of the first semiconductor fin.

14. The integrated circuit of claim 13, wherein the first top width is substantially equal to the second top width.

15. The integrated circuit of claim 13, wherein the first top width is substantially equal to the first bottom width.

16. The integrated circuit of claim 13, wherein the second bottom width is greater than the second top width.

17. The integrated circuit of claim 13, wherein the first top width is greater than the first bottom width.

18. The integrated circuit of claim 13, wherein the second top width is substantially equal to the second bottom width.

19. An integrated circuit comprising:

a substrate;

at least one n-type semiconductor device present on the substrate, wherein;

the n-type semiconductor device comprises a first semiconductor fin,

the n-type semiconductor device comprises a first gate structure having;

a first sidewall that comprises a first non-tapered, vertical portion overlying a first top surface of the first semiconductor fin and extending from a second top surface of the first gate structure overlying the first top surface to a first bottom surface of the first gate structure overlying the first top surface; and

a second sidewall that comprises a second non-tapered, vertical portion overlying the first top surface and extending from the second top surface to the first bottom surface; and

at least one p-type semiconductor device present on the substrate, wherein;

the p-type semiconductor device comprises a second semiconductor fin,

the p-type semiconductor device comprises a second gate structure having;

a third sidewall that comprises a third non-tapered, vertical portion overlying a third top surface of the second semiconductor fin and a first tapered portion overlying the third top surface; and

a fourth sidewall that comprises a fourth non-tapered, vertical portion overlying the third top surface and a second tapered portion overlying the third top surface,

a second cross-sectional area of the second gate structure at a top of the second semiconductor fin is larger than a first cross-sectional area of the first gate structure at a top of the first semiconductor fin,

the third non-tapered, vertical portion extends from a fourth top surface of the second gate structure overlying the third top surface to the first tapered portion,

the fourth non-tapered, vertical portion extends from the fourth top surface to the second tapered portion,

the first tapered portion extends from the third non-tapered, vertical portion to a second bottom surface of the second gate structure overlying the third top surface, and

the second tapered portion extends from the fourth non-tapered, vertical portion to the second bottom surface.

20. The integrated circuit of claim 19, wherein:

the first gate structure consists of a first number of layers greater than one,

the second gate structure consists of a second number of layers greater than one, and

the second numbers of layers is greater than the first number of layers.