Sloped finFET with methods of forming same

• US 9,985,112 B2
• Filed: 02/06/2015
• Issued: 05/29/2018
• Est. Priority Date: 02/06/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Anderson, Brent A., Nowak, Edward J.
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Kim, Tong-Ho
• Application Number:
  US14/616,018
• Publication Number:
  US 20160233246A1
• Time in Patent Office: 1,208 Days
• Field of Search: 257347, 438586
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.

Claims

1. A method of forming an integrated circuit (IC) structure, the method comprising:

forming a semiconductor fin, the semiconductor fin including an initial geometry;

forming a sacrificial gate on the semiconductor fin;

forming a first spacer on the semiconductor fin, the first spacer positioned circumferentially about the sacrificial gate;

forming a second spacer on the semiconductor fin, the second spacer positioned circumferentially about the first spacer;

tapering a first portion of the semiconductor fin to form sloped sidewalls, the first portion of the semiconductor exposed and adjacent the sacrificial gate, the first spacer and the second spacer;

selectively removing the sacrificial gate from the semiconductor fin to expose a second region of the semiconductor fin;

reducing a width of the second region of the semiconductor fin; and

forming a gate dielectric on the second region of the semiconductor fin,

wherein the first spacer and the second spacer are positioned circumferentially above the second region of the semiconductor fin.

2. The method of claim 1, further comprising:

reducing a height of the second region of the semiconductor fin, the height of the second region of the semiconductor fin less than;

a height of the initial geometry of the semiconductor fin; and

a height of the first portion of the semiconductor fin.

3. The method of claim 2, wherein forming the first spacer includes:

covering a portion of a third region of the semiconductor fin, the third region of the semiconductor fin including the initial geometry of the semiconductor fin.

4. The method of claim 3, wherein forming the second spacer includes:

covering a remaining portion of the third region of the semiconductor fin.

5. The method of claim 1, further comprising:

forming a source contact on the sloped sidewalls of the first portion of the semiconductor fin, the source contact formed outside of the first spacer and the second spacer; and

forming a drain contact on the sloped sidewalls of the first portion of the semiconductor fin, opposite the source contact, the drain contact formed outside of the first spacer and the second spacer.