Method for manufacturing semiconductor device

• US 9,985,118 B2
• Filed: 06/27/2016
• Issued: 05/29/2018
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sasaki, Toshinari, Sakata, Junichiro, Ohara, Hiroki, Yamazaki, Shunpei
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US15/193,827
• Publication Number:
  US 20160308035A1
• Time in Patent Office: 701 Days
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of:

forming a first oxide semiconductor layer;

forming a second oxide semiconductor layer over the first oxide semiconductor layer;

performing a first heat treatment on the first oxide semiconductor layer and the second oxide semiconductor layer under an atmosphere comprising nitrogen to be dehydrated or dehydrogenated, wherein the first oxide semiconductor layer has a carrier density of 1×

10¹⁸/cm³ or more;

forming an oxide insulating layer over and in contact with a part of the first oxide semiconductor layer and the second oxide semiconductor layer; and

performing a second heat treatment on the oxide insulating layer,

wherein the first oxide semiconductor layer has a carrier density of less than 1×

10¹⁸/cm³ after the second heat treatment.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the first heat treatment is performed at 400°

C. or higher.

3. The method for manufacturing a semiconductor device according to claim 1, wherein a temperature of the second heat treatment is lower than a temperature of the first heat treatment.

4. The method for manufacturing a semiconductor device according to claim 1, wherein a cooling is performed under an atmosphere including oxygen after the first heat treatment.

5. The method for manufacturing a semiconductor device according to claim 1, wherein one of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc.

6. The method for manufacturing a semiconductor device according to claim 1, wherein one of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, tin, and zinc.

7. The method for manufacturing a semiconductor device according to claim 1, wherein one of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, aluminum, and zinc.

8. The method for manufacturing a semiconductor device according to claim 1, wherein one of the first oxide semiconductor layer and the second oxide semiconductor layer comprises tin and zinc.

9. The method for manufacturing a semiconductor device according to claim 1, wherein one of the first oxide semiconductor layer and the second oxide semiconductor layer comprises tin, gallium, and zinc.

10. The method for manufacturing a semiconductor device according to claim 1, wherein one of the first oxide semiconductor layer and the second oxide semiconductor layer comprises tin, aluminum, and zinc.

11. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide insulating layer is in contact with a side surface of the second oxide semiconductor layer.

12. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the second oxide semiconductor layer is smaller than a thickness of the first oxide semiconductor layer.