Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors
First Claim
1. A method for forming a semiconductor structure, the method comprising:
- forming a structure comprising at least an alternating stack of semiconductor layers and metal gate material layers formed on a substrate, a metal gate formed on and in contact with a top layer of the alternating stack, a source region and a drain region in contact with the semiconductor layers of the alternating stack, and dielectric layers formed on and in contact with a top surface of the source and drain regions, respectively;
removing a portion of the semiconductor layers and metal gate material layers, wherein the removing forms a trench exposing sidewalls of the metal gate and sidewalls of the source and drain regions;
epitaxially growing a first plurality of interconnects between and in contact with the semiconductor layers and the source region; and
epitaxially growing a second plurality of interconnects between and in contact with the semiconductor layers and the drain region,wherein epitaxially growing the first and second plurality of interconnects forms air pockets between the metal gate material layers and the source region, and between the metal gate material layers and the drain region.
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Accused Products
Abstract
A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.
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Citations
19 Claims
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1. A method for forming a semiconductor structure, the method comprising:
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forming a structure comprising at least an alternating stack of semiconductor layers and metal gate material layers formed on a substrate, a metal gate formed on and in contact with a top layer of the alternating stack, a source region and a drain region in contact with the semiconductor layers of the alternating stack, and dielectric layers formed on and in contact with a top surface of the source and drain regions, respectively; removing a portion of the semiconductor layers and metal gate material layers, wherein the removing forms a trench exposing sidewalls of the metal gate and sidewalls of the source and drain regions; epitaxially growing a first plurality of interconnects between and in contact with the semiconductor layers and the source region; and epitaxially growing a second plurality of interconnects between and in contact with the semiconductor layers and the drain region, wherein epitaxially growing the first and second plurality of interconnects forms air pockets between the metal gate material layers and the source region, and between the metal gate material layers and the drain region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for forming a semiconductor structure, the method comprising:
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forming an alternating stack of semiconductor layers and metal gate material layers on a substrate; forming a metal gate on and in contact with a top layer of the alternating stack; removing a portion of the semiconductor layers and metal gate material layers, wherein the removing forms a first trench and a second trench; epitaxially growing a first plurality of interconnects within the first trench, wherein each interconnect in first plurality of interconnects contacts a semiconductor layer of the alternating stack, the epitaxially growing forming air pockets between pairs of interconnects in the first plurality of interconnects; and epitaxially growing a second plurality of interconnects within the first trench, wherein each interconnect in second plurality of interconnects contacts a semiconductor layer of the alternating stack, the epitaxially growing forming air pockets between pairs of interconnects in the second plurality of interconnects. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification