Digital duty cycle correction for frequency multiplier

• US 9,985,618 B2
• Filed: 05/12/2016
• Issued: 05/29/2018
• Est. Priority Date: 12/23/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Park, Dongmin, Park, Jong Min, Leung, Lai Kan
• Primary Examiner(s): Cadeau, Wednel
• Application Number:
  US15/153,496
• Publication Number:
  US 20170187364A1
• Time in Patent Office: 747 Days
• Field of Search: 375355, 375326, 375300
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0332 with an integrator-detector

Abstract

An apparatus includes a phase detector coupled to an output of a frequency multiplier. A digital loop filter is coupled to the phase detector, and a duty cycle correction circuit is coupled to the digital loop filter.

Claims

1. An apparatus comprising:

a phase detector coupled to an output of a frequency multiplier;

a digital loop filter coupled to the phase detector;

a duty cycle correction circuit coupled to the digital loop filter, the duty cycle correction circuit configured to receive an input signal as a first input and configured to receive a control signal from the digital loop filter as a second input;

a logic gate of the phase detector, the logic gate coupled to the digital loop filter and to the duty cycle correction circuit; and

a reference signal generator coupled to the output of the frequency multiplier and coupled to an input of the phase detector, wherein the reference signal generator includes a delay locked loop and a charge pump.

2. The apparatus of claim 1, the frequency multiplier comprising a frequency doubler coupled to the duty cycle correction circuit and to the phase detector, the duty cycle correction circuit having an output coupled to an input of the frequency multiplier.

3. The apparatus of claim 1, the phase detector comprising a bang bang phase detector and the logic gate, the duty cycle correction circuit configured to adjust a duty cycle of the input signal based on the control signal.

4. The apparatus of claim 1, the digital loop filter comprising a digital accumulator.

5. The apparatus of claim 1, the reference signal generator further comprising a phase frequency detector, the phase frequency detector coupled to the delay locked loop and to the charge pump, wherein the reference signal generator is coupled to a D flip flop circuit of the phase detector.

6. The apparatus of claim 1, wherein the logic gate has a first input coupled to an output of the duty cycle correction circuit, a second input coupled to an output of a bang bang phase detector of the phase detector, and an output coupled to an input of the digital loop filter.

7. The apparatus of claim 3, the bang bang phase detector comprising a D flip flop circuit.

8. The apparatus of claim 5, further comprising an accumulator coupled to the charge pump.

9. The apparatus of claim 6, wherein the logic gate comprises an XNOR gate, wherein the XNOR gate is configured to receive a duty cycle adjusted signal from the duty cycle correction circuit and an output signal from the bang bang phase detector, and wherein the XNOR gate is configured to output a phase detector output signal to the digital loop filter.

10. The apparatus of claim 8, the accumulator coupled to an output of the phase detector.

11. The apparatus of claim 9, further comprising a second digital loop filter coupled to the phase detector, wherein an input of the second digital loop filter is coupled to the output of the phase detector and to the second input of the XNOR gate.

12. An apparatus comprising:

means for detecting a phase of an output signal of means for multiplying a frequency;

means for digitally filtering a signal, the means for digitally filtering coupled to the means for detecting;

means for correcting a duty cycle coupled to the means for digitally filtering and to the means for multiplying the frequency, the means for correcting the duty cycle configured to receive an input signal as a first input and configured to receive a control signal from the means for digitally filtering the signal as a second input;

means for generating a phase detector output signal coupled to the means for digitally filtering the signal and to the means for correcting the duty cycle; and

means for generating a reference signal, the means for generating the reference signal coupled to an input of the means for detecting and coupled to the output of the means for multiplying, the means for generating the reference signal including means for generating a delayed signal and means for providing a voltage.

13. The apparatus of claim 12, the means for multiplying the frequency coupled to the means for correcting the duty cycle and to the means for detecting.

14. The apparatus of claim 12, the means for detecting comprising means for generating a binary phase detection signal and the means for generating the phase detector output signal, the means for generating a binary phase detection signal comprising means for latching data.

15. The apparatus of claim 12, the means for digitally filtering comprising means for digitally accumulating phase detection, wherein the means for generating the phase detector output signal comprises an XNOR gate.

16. The apparatus of claim 12, the means for generating the reference signal further including means for detecting a phase difference between the output signal and the reference signal.

17. The apparatus of claim 16, further comprising means for filtering an output of the means for detecting and for providing a control signal to the means for providing a voltage.

18. A method comprising:

generating an output signal having a second frequency that is a multiple of a first frequency of an input signal;

generating a reference signal, the reference signal having a delay relative to the output signal;

generating a phase detection signal based on the output signal, the reference signal, and based on a duty cycle adjusted signal;

digitally filtering the phase detection signal to generate a control signal; and

adjusting a duty cycle of the input signal based on the control signal to update the duty cycle adjusted signal, the updated duty cycle adjusted signal provided to a frequency multiplier.

19. The method of claim 18, wherein generating the phase detection signal includes:

generating an intermediary signal based on a timing of the output signal and sampled values of the reference signal; and

comparing the intermediary signal to the duty cycle adjusted signal to generate the phase detection signal.

20. The method of claim 18, further comprising generating a charge pump mismatch signal based on the phase detection signal.