System for reducing noise in a chemical sensor array

• US 9,985,624 B2
• Filed: 02/22/2016
• Issued: 05/29/2018
• Est. Priority Date: 05/29/2012
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Jordan, Jeremy, Rearick, Todd
• Primary Examiner(s): Cole, Brandon S
• Application Number:
  US15/049,462
• Publication Number:
  US 20160173080A1
• Time in Patent Office: 827 Days
• Field of Search: 327165, 327166, 327291-299, 327374, 327178, 326 93- 98, 716 6
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents

Abstract

A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal.

Claims

1. A system comprising:

a power supply;

a clock circuitry operably coupled to the power supply, the clock circuitry configured to generate a plurality of clock signals, each clock signal of the plurality of clock signals being synchronous with a primary clock signal and each clock signal having a cycle that spans multiple cycles of the primary clock signal; and

a plurality of switchers operably coupled to receive the plurality of clock signals, wherein the plurality of switchers comprises;

a first set of switchers having a low power draw, and

a second set of switchers having a high power draw,

wherein the clock circuitry is further configured to;

supply a first group of the plurality of clock signals to the first set of switchers;

offset each clock signal in the first group from each other by a first number of cycles of the primary clock signal;

supply a second group of the plurality of clock signals to the second set of switchers; and

offset each clock signal in the second group from each other by a second number of cycles of the primary clock signal,

wherein the second number of cycles of the primary clock signal for the offset of each clock signal in the second group is larger than the first number of cycles of the primary clock signal for the offset of each clock signal in the first group.

2. The system of claim 1, wherein the plurality of switchers is disposed on a substrate.

3. The system of claim 1, further comprising a linear regulator coupled each switcher.

4. The system of claim 1, wherein each of the plurality of clock signals has a different frequency.

5. The system of claim 4, wherein the first group comprises at least a first clock signal, a second clock signal, and a third clock signal, and a first frequency of the first clock signal is greater than a second frequency of the second clock signal and the second frequency of the second clock signal is greater than a third frequency of the third clock signal, wherein the first frequency of the first clock signal is a first multiple of the second frequency of the second clock signal and is a second multiple of the third frequency of the third clock signal.

6. The system of claim 5, wherein the second frequency of the second clock signal is a third multiple of the third frequency of the third clock signal.

7. The system of claim 5, wherein a rising edge of the first clock signal is offset by at least 1/2 cycle of the primary clock signal from a rising edge of the second clock signal.

8. The system of claim 5, wherein a rising edge of the first clock signal is offset in a range of 1/2 to (n−

1)/2 cycles of the primary clock signal, where “

n”

is the number of cycles of the primary clock signal in a cycle of the second clock signal.

9. The system of claim 1, wherein at least two clock signals from the first group have the same frequency.

10. The system of claim 9, wherein the at least two clock signals are offset by at least 1/2 cycles of the primary clock signal.

11. The system of claim 9, wherein at least two clock signals from the second group are offset by at least two cycles of the primary clock signal.

12. A method of providing power to a circuitry, the method comprising:

supplying power with a power supply to a plurality of switchers, wherein a first set of the plurality of switchers has a low power draw and a second set of the plurality of switchers has a high power draw;

generating a plurality of clock signals with a clock circuitry operably coupled to the plurality of switchers, each clock signal of the plurality of clock signals being synchronous with a primary clock signal and each clock signal of the plurality of clock signals having a cycle that spans multiple cycles of the primary clock signal;

supplying a first group of the plurality of clock signals to the first set of switchers;

offsetting each clock signal in the first group from each other by a first number of cycles of the primary clock signal;

supplying a second group of the plurality of clock signals to the second set of switchers; and

offsetting each clock signal in the second group from each other by a second number of cycles of the primary clock signal,

wherein the second number of cycles of the primary clock signal for the offsetting of each clock signal in the second group is larger than the first number of cycles of the primary clock signal for the offsetting of each clock signal in the first group.

13. The method of claim 12, further comprising coupling a linear regulator to each switcher.

14. The method of claim 12, wherein the first group comprises at least a first clock signal, a second clock signal, and a third clock signal, and a first frequency of the first clock signal is greater than a second frequency of the second clock signal and the second frequency of the second clock signal is greater than a third frequency of the third clock signal, wherein the first frequency of the first clock signal is a first multiple of the second frequency of the second clock signal and is a second multiple of the third frequency of the third clock signal.

15. The method of claim 14, wherein a rising edge of the first clock signal is offset in a range of 1/2 to (n−

1)/2 cycles of the primary clock signal, where “

n”

is the number of cycles of the primary clock signal in a cycle of the second clock signal.

16. The method of claim 14, wherein the frequency of the second clock signal is a third multiple of the frequency of the third clock signal.

17. The method of claim 12, wherein each clock signal in the second group has a different frequency.