Vector signaling with reduced receiver complexity

• US 9,985,745 B2
• Filed: 06/27/2017
• Issued: 05/29/2018
• Est. Priority Date: 06/25/2013
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin
• Primary Examiner(s): Flores, Leon
• Application Number:
  US15/635,012
• Publication Number:
  US 20170294985A1
• Time in Patent Office: 336 Days
• CPC Class Codes: H03M 5/02 Conversion to or from representation by pulses
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 17/18 Code selection mechanisms

Abstract

Methods and apparatuses are described to determine subsets of vector signaling codes capable of detection by smaller sets of comparators than required to detect the full code. The resulting lower receiver complexity allows systems utilizing such subset codes to be less complex and require less power.

Claims

1. An apparatus comprising:

an arithmetic unit connected to a plurality of wires of a multi-wire bus comprising four wires, the arithmetic unit comprising at least first and second averaging units connected to first and second pairs of wires of the multi-wire bus, respectively, the first and second pairs of wires being disjoint, the first and second pairs of wires carrying permutations of base vectors (1,0) and (0,−

1), respectively, the first and second averaging units configured to generate first and second common mode values respectively based on averages of the base vectors carried by the first and second pairs of wires, respectively; and

a comparator unit comprising a two-input comparator configured to receive the first and second common mode values from the arithmetic unit, and to responsively form a binary output representing a common mode difference between the received first and second common mode values, the binary output used at least in part in determining a set of output bits.

2. The apparatus of claim 1, wherein the permutations of the base vectors on the first and second pairs of wires of the multi-wire bus correspond to a codeword of a vector signaling code.

3. The apparatus of claim 1, further comprising a sparse comparator unit connected to the multi-wire bus configured to generate second and third binary outputs.

4. The apparatus of claim 3, wherein the sparse comparator unit comprises first and second local two-input comparators connected to the first and second pairs of wires of the multi-wire bus, respectively.

5. The apparatus of claim 1, wherein the first and second pairs of wires are adjacent wires.

6. A method comprising:

receiving a plurality of signals via wires of a multi-wire bus comprising four wires;

generating first and second common mode values using first and second averaging units, the first and second averaging units receiving permutations of base vectors (1,0) and (0,−

1) on the first and second pairs of wires of the multi-wire bus, respectively, the first and second pairs of wires being disjoint, the first and common mode values corresponding to averages of the base vectors carried by the first and second pairs of wires, respectively; and

forming a binary output at a comparator unit comprising a two-input comparator, the comparator unit receiving the first and second common mode values from the first and second averaging units, the binary output representing common mode difference between the received first and second common mode values, the binary output used at least in part in determining a set of output bits.

7. The method of claim 6, wherein the permutations of the base vectors on the first and second pairs of wires correspond to symbols of a codeword of a vector signaling code.

8. The method of claim 6, further comprising generating second and third binary outputs using a sparse comparator unit connected to the multi-wire bus.

9. The method of claim 8, wherein the sparse comparator unit comprises first and second local two-input comparators connected to the first and second pairs of wires of the multi-wire bus, respectively.

10. The method of claim 6, wherein the first and pairs of wires are to adjacent wires.