Systems and methods for processing errors of a received signal

• US 9,985,804 B2
• Filed: 06/08/2016
• Issued: 05/29/2018
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Cyrusian, Sasan
• Primary Examiner(s): Vallecillo, Kyle
• Application Number:
  US15/176,492
• Publication Number:
  US 20160285655A1
• Time in Patent Office: 720 Days
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

A receiver includes a first sampler configured to sample, according to a first clock signal, a received signal including first data and second data and output first samples corresponding to the first data of the received signal. A first data comparator is configured to receive, from the first sampler, the first samples corresponding to the first data of the received signal and generate, based on the first clock signal, a first digital data output corresponding to the first data of the received signal. A first error comparator is configured to receive, from the first sampler, the first samples corresponding to the first data of the received signal and generate, based on the first clock signal, a first digital error output corresponding to the first data of the received signal and a first error associated with the first data of the received signal.

Claims

1. A receiver, comprising:

a first sampler arranged to receive a first clock signal and a received signal, wherein the received signal includes first and second data and corresponds to an input signal received from a communication channel, and wherein the first sampler is configured to (i) sample, according to the first clock signal, the received signal and (ii) output first samples corresponding to the first data of the received signal;

a first data comparator arranged to receive the first clock signal and coupled to an output of the first sampler, wherein the first data comparator is configured to

receive, from the first sampler, the first samples corresponding to the first data of the received signal,

modify the first samples according to a first feedback signal, and

convert, according to the first clock signal, the modified first samples to a first digital data output corresponding to the first data of the received signal; and

a first error comparator arranged to receive the first clock signal and coupled to the output of the first sampler, wherein the first error comparator is configured to

receive, from the first sampler, the first samples corresponding to the first data of the received signal,

modify the first samples according to a second feedback signal, and

convert, according to the first clock signal, the modified second samples to a first digital error output corresponding to (a) the first data of the received signal and (b) a first error associated with the first data of the received signal,

wherein the first data comparator and the first error comparator are arranged to receive the first samples from the same first sampler.

2. The receiver of claim 1, further comprising:

a second sampler configured to (i) sample, according to a second clock signal having a different phase than the first clock signal, the received signal and (ii) output second samples corresponding to the second data of the received signal;

a second data comparator configured to (i) receive, from the second sampler, the second samples corresponding to the second data of the received signal and (ii) generate, based on the second clock signal, a second digital data output corresponding to the second data of the received signal; and

a second error comparator configured to (i) receive, from the second sampler, the second samples corresponding to the second data of the received signal and (ii) generate, based on the second clock signal, a second digital error output corresponding to (a) the second data of the received signal and (b) a second error associated with the second data of the received signal.

3. The receiver of claim 2, wherein the first clock signal and the second clock signal have a phase difference of approximately 180 degrees.

4. The receiver of claim 2, wherein the first clock signal corresponds to an odd clock signal and the second clock signal corresponds to an even clock signal.

5. The receiver of claim 1, further comprising a digital adaptation module configured to generate (i) the first feedback signal based on the first digital data output, wherein the first data comparator is configured to generate the first digital data output further based on the first feedback signal and (ii) the second feedback signal based on the first digital error output, wherein the first error comparator is configured to generate the first digital error output further based on the second feedback signal.

6. The receiver of claim 5, wherein (i) the first data comparator includes a first decision feedback estimator configured to modify the first samples according to the first feedback signal and (ii) the first error comparator includes a second decision feedback estimator configured to modify the first samples according to the second feedback signal.

7. The receiver of claim 6, wherein the digital adaptation module is configured to generate a third feedback signal, and wherein the receiver further comprises a third decision feedback estimator configured to modify the first samples according to the third feedback signal.

8. The receiver of claim 6, wherein, to generate the first digital data output, the first data comparator is configured to sum an output of the first decision feedback estimator with the modified first samples, and wherein, to generate the first digital error output, the first error comparator is configured to sum an output of the second decision feedback estimator with the modified first samples.

9. A method of operating a receiver, the method comprising:

using a first sampler arranged to receive a first clock signal and a received signal, wherein the received signal includes first and second data and corresponds to an input signal received from a communication channel,

sampling, according to the first clock signal, the received signal, and

outputting first samples corresponding to the first data of the received signal;

using a first data comparator arranged to receive the first clock signal and coupled to an output of the first sampler,

modifying the first samples according to a first feedback signal, and

converting, according to the first clock signal, the modified first samples to a first digital data output corresponding to the first data of the received signal; and

using a first error comparator arranged to receive the first clock signal and coupled to the output of the first sampler,

modifying the first samples according to a second feedback signal, and

converting, according to the first clock signal, the modified first samples to a first digital error output corresponding to (a) the first data of the received signal and (b) a first error associated with the first data of the received signal,

wherein the first digital data output and the first digital error output are generated using the first samples received from the same first sampler.

10. The method of claim 9, further comprising:

sampling, according to a second clock signal having a different phase than the first clock signal, the received signal;

outputting second samples corresponding to the second data of the received signal;

generating, based on the second clock signal and the second samples corresponding to the second data of the received signal, a second digital data output corresponding to the second data of the received signal; and

generating, based on the second clock signal and the second samples corresponding to the second data of the received signal, a second digital error output corresponding to (a) the second data of the received signal and (b) a second error associated with the second data of the received signal.

11. The method of claim 10, wherein the first clock signal and the second clock signal have a phase difference of approximately 180 degrees.

12. The method of claim 10, wherein the first clock signal corresponds to an odd clock signal and the second clock signal corresponds to an even clock signal.

13. The method of claim 9, further comprising generating (i) the first feedback signal based on the first digital data output, wherein the first digital data output is generated further based on the first feedback signal and (ii) the second feedback signal based on the first digital error output, wherein the first digital error output is generated further based on the second feedback signal.

14. The method of claim 9, further comprising generating a third feedback signal and modifying the first samples according to the third feedback signal.

15. The method of claim 9, wherein generating the first digital data output includes summing an output based on the first feedback signal with the modified first samples, and wherein generating the first digital error output includes summing an output based on the second feedback signal with the modified first samples.