Scalable and area optimized method to implement command queues in SRIOV based NVM devices

• US 9,990,139 B2
• Filed: 01/04/2016
• Issued: 06/05/2018
• Est. Priority Date: 04/16/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Nadakuditi, Srinivasa Raju, Sampath, Madhusudan, Kunnumpurathu Sivan, Sarath Kumar
• Primary Examiner(s): Zaman, Faisal M
• Application Number:
  US14/987,045
• Publication Number:
  US 20160306549A1
• Time in Patent Office: 883 Days
• Field of Search: 710 9, 710 5, 710 72, 710 74, 710313, 711103, 711114
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2009/45579 I/O management, e.g. providing access to device drivers or storage
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/44 Arrangements for executing specific programs
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: H04L 41/0654 using network fault recovery ring fault isolation or reconfiguration in loop networks without recovery actions by a network management system H04L12/437
• CPC Class Codes: H04L 41/0681 Configuration of triggering conditions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Provided are method for dynamically allocating resources to command queues and response queues by a non-volatile memory (NVM) controller. The method includes creating command queues and response queues for at least one operating system among a plurality of operating systems running on a host system and mapping the created command queues and response queues to a plurality of internal shared queue registers. The plurality of operating systems running on the host system communicate with at least one NVM controller independently.

Claims

1. A method for dynamically allocating resources to command queues and response queues by a non-volatile memory (NVM) controller, the method comprising:

mapping, by the NVM controller, first input queues associated with a first operating system (OS) running on a host system to first registers of an NVM device for creating first command queues and first response queues; and

mapping, by the NVM controller, second input queues associated with a second OS running on the same host system to the same first registers so that the second OS shares the created first command queues and first response queues,

wherein the operating systems running on the host system communicate with at least one NVM controller independently.

2. The method of claim 1, wherein the first command queues and first response queues are created using inputs from one of:

at least one physical function (PF) and at least one virtual function (VF) that a Single Root I/O Virtualization (SRIOV) specification.

3. The method of claim 1, wherein the mapping of the second input queues occurs when creating additional command and response queues based on the second input queues exceeds a number of queues supported by the NVM device.

4. The method of claim 3, wherein the NVM controller is located within the NVM device.

5. The method of claim 1, wherein each operating system is managed by a different virtual machine running on the host system.

18. The method of claim 3, further comprising:

mapping, by the NVM controller, the second input queues associated with the second OS to second registers of the NVM device for creating second command queues and second response queues when creating additional command and response queues based on the second input queues does not exceed the number of queues supported by the NVM device.

6. An apparatus for dynamically allocating resources to command queues and response queues, the apparatus comprising:

a non-volatile memory (NVM) controller configured to map first input queues associated with a first operating system (OS) running on a host system to first registers of a NVM device to create first command queues and first response queues, and map second input queues associated with a second OS running on the same host system to the same first registers so that the second OS shares the created first command queues and first response queues,

wherein the operating systems running on the host system communicate with at least one NVM controller independently.

7. The NVM controller of claim 6, wherein the first command queues and first response queues are created using inputs from one of:

at least one physical function (PF) and at least one virtual function (VF) that support a Single Root I/O Virtualization (SRIOV) specification.

8. The NVM controller of claim 6, wherein the mapping of the second input queues occurs when creating additional command and response queues based on the second input queues exceeds a number of queues supported by the NVM device.

9. The NVM controller of claim 8, wherein the NVM controller is located within the NVM device.

10. The NVM controller of claim 6, wherein each operating system is managed by a different virtual machine running on the host system.

19. The apparatus of claim 6, wherein the NVM controller maps the second input queues associated with the second OS to second registers of the NVM device for creating second command queues and second response queues when creating additional command and response queues based on the second input queues does not exceed a number of queues supported by the NVM device.

11. A system configured to manage a plurality of virtual machines, the system comprising:

a host computer comprising a host operating system, and a hypervisor configured to manage a first virtual machine comprising a first guest operating system and a first virtual function driver and a second virtual machine comprising a second guest operating system and a second virtual function driver;

a non-volatile memory (NVM),

wherein the NVM comprises a controller configured to create first queues using a plurality of registers of the NVM, and map the first virtual function driver and the second virtual function driver to the same first queues stored in the plurality of registers when creation of additional queues for the second quest operating system exceeds a number of queues supported by the NVM.

12. The system of claim 11, wherein the NVM is configured to support a Single Root I/O Virtualization (SRIOV) specification.

13. The system of claim 11, the first queues comprise at least one command queue configured to store a command to be executed by one of the guest operating systems and a response queue configured to store a result of executing the command.

14. The system of claim 11, wherein the first queues are created using an input from a virtual function of one of the virtual function drivers that is compatible with a Single Root I/O Virtualization (SRIOV) specification.

15. The system of claim 14, wherein one of the virtual function drivers uses descriptors to communicate with the virtual function to inform the virtual function where to copy data to and from a host memory of the host computer.

16. The system of claim 11, wherein the first queues are created using an input from a physical function of a physical function driver of the host computer that is compatible with a Single Root I/O Virtualization (SRIOV) specification.

17. The system of claim 11, further comprising a PCIe root complex configured to interface with the hypervisor and the NVM.