Memory device for internally performing read-verify operation, method of operating the same, and memory system including the same

• US 9,990,149 B2
• Filed: 01/18/2016
• Issued: 06/05/2018
• Est. Priority Date: 02/06/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Taek Kyun, Kim, Hyun Ju
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): Wong, Nanci N
• Application Number:
  US14/997,888
• Publication Number:
  US 20160231953A1
• Time in Patent Office: 869 Days
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A method of operating a memory device includes writing initial data to non-volatile memory cells of a non-volatile memory cell array, generating a difference value based on a difference between first data related to the initial data written to the non-volatile memory cells and second data related to the initial data written to the non-volatile memory cells, comparing the difference value with a reference value, and generating and transmitting a status signal indicating that the initial data has been successfully written to a controller when the difference value is less than the reference value. The data may be randomized by the controller or the memory device.

Claims

1. A method of operating a memory device, comprising:

writing initial data to non-volatile memory cells of a non-volatile memory cell array;

generating a difference value based on a difference between first data related to the initial data written to the non-volatile memory cells and second data related to the initial data written to the non-volatile memory cells;

comparing the difference value with a reference value;

generating a status signal having a first state indicating that the initial data has been successfully written when the difference value is less than the reference value, and having a second state indicating that the initial data has not been successfully written when the difference value is equal to or greater than the reference value;

performing a read-verify operation on the initial data, by the memory device, when the status signal has the first state;

transmitting the status signal to a controller; and

transmitting the initial data to the controller when the status signal has the second state,

wherein the status signal causes the controller to perform the read-verify operation on the initial data when the status signal has the second state.

2. The method of claim 1, wherein the initial data is randomized by one of the controller and the memory device.

3. The method of claim 1, wherein generating the difference value comprises:

reading the initial data from the non-volatile memory cells;

generating the first data and the second data based on the initial data that has been read, wherein the first data corresponds to a number of on-cells from among the non-volatile memory cells and the second data corresponds to a number of off-cells from among the non-volatile memory cells; and

calculating the difference value using the first data and the second data.

4. The method of claim 1, wherein writing the initial data comprises:

writing the initial data to the non-volatile memory cells using a first buffer,

wherein the first data is obtained by copying the initial data stored in the first buffer to a second buffer, the second data is obtained by reading the initial data from the non-volatile memory cells and subsequently storing the initial data in the first buffer, and the difference value is a number of bitwise differences between values of the first data stored in the second buffer and corresponding values of the second data stored in the first buffer.

5. The method of claim 1, wherein writing the initial data comprises:

writing the initial data to the non-volatile memory cells using a first buffer,

wherein the first data is obtained by storing the initial data in the first buffer, the second data is obtained by reading the initial data from the non-volatile memory cells and subsequently storing the initial data in a second buffer, and the difference value is a number of bitwise differences between values of the first data stored in the first buffer and corresponding values of the second data stored in the second buffer.

6. The method of claim 1, wherein writing the initial data comprises:

writing the initial data to the non-volatile memory cells using a first buffer,

wherein the first data is obtained by copying the initial data stored in the first buffer to a second buffer, the second data is obtained by reading the initial data from the non-volatile memory cells and subsequently storing the initial data in a third buffer, and the difference value is a number of bitwise differences between values of the first data stored in the second buffer and corresponding values of the second data stored in the third buffer.

7. The method of claim 1, wherein writing the initial data comprises:

writing the initial data to the non-volatile memory cells using a second buffer,

wherein the first data is obtained by copying the initial data from a first buffer to the second buffer, the second data is obtained by reading the initial data from the non-volatile memory cells and subsequently storing the initial data in a third buffer, and the difference value is a number of bitwise differences between values of the first data stored in the second buffer and corresponding values of the second data stored in the third buffer.

8. The method of claim 1, wherein the reference value is written to the memory device by the controller.

9. The method of claim 1, wherein the reference value is determined based on at least one of program/erase cycles and a read count with respect to the non-volatile memory cells.

10. The method of claim 1, wherein the initial data is metadata related to an operation of the memory device, and the metadata is stored in the non-volatile memory cells using single-level cell programming when each of the non-volatile memory cells is a multi-level cell storing information of at least two bits.

11. The method of claim 1, wherein the non-volatile memory cell array is a three-dimensional memory cell array and each of the non-volatile memory cells comprises a charge trap layer.

12. A memory device, comprising:

a non-volatile memory cell array comprising non-volatile memory cells, wherein initial data output from a controller is written to the non-volatile memory cells;

a difference value generation circuit configured to generate a difference value based on a difference between first data related to the initial data written to the non-volatile memory cells and second data related to the initial data written to the non-volatile memory cells;

a register configured to store a reference value; and

a comparator configured to compare the difference value with the reference value stored in the register and to generate a status signal having a first state indicating that the initial data has been successfully written when the difference value is less than the reference value, and having a second state indicating that the initial data has not been successfully written when the difference value is equal to or greater than the reference value,

wherein a read-verify operation is performed on the initial data, by the memory device, when the status signal has the first state,

wherein the status signal causes the controller to perform the read-verify operation on the initial data when the status signal has the second state.

13. The memory device of claim 12, wherein the difference value generation circuit comprises:

a page buffer configured to store the initial data read from the non-volatile memory cells;

an on-cell counter configured to generate the first data based on the initial data stored in the page buffer, wherein the first data corresponds to a number of on-cells from among the non-volatile memory cells;

an off-cell counter configured to generate the second data based on the initial data stored in the page buffer, wherein the second data corresponds to a number of off-cells from among the non-volatile memory cells; and

a subtractor configured to calculate the difference value using the first data and the second data.

14. The memory device of claim 12, wherein the difference value generation circuit comprises:

a first buffer configured to store the first data related to the initial data written to the non-volatile memory cells;

a second buffer configured to store the first data copied from the first buffer; and

a data comparator configured to calculate a number of differences between values of the first data output from the second buffer and corresponding values of the second data output from the first buffer, wherein the first buffer stores the second data read from the non-volatile memory cells, and to generate the difference value.

15. The memory device of claim 12, wherein the difference value generation circuit comprises:

a first buffer configured to store the first data related to the initial data written to the non-volatile memory cells;

a second buffer configured to store the second data read from the non-volatile memory cells; and

a data comparator configured to calculate a number of differences between values of the first data stored in the first buffer and corresponding values of the second data stored in the second buffer, and to generate the difference value.

16. The memory device of claim 12, wherein the difference value generation circuit comprises:

a first buffer configured to store the first data related to the initial data written to the non-volatile memory cells;

a second buffer configured to store the first data copied from the first buffer;

a third buffer configured to store the second data read from the non-volatile memory cells; and

a data comparator configured to calculate a number of differences between values of the first data stored in the second buffer and corresponding values of the second data stored in the third buffer, and to generate the difference value.

17. The memory device of claim 12, wherein the difference value generation circuit comprises:

a first buffer configured to receive the first data;

a second buffer configured to store the first data, wherein the first data is copied from the first buffer and is subsequently written to the non-volatile memory cells;

a third buffer configured to store the second data read from the non-volatile memory cells; and

a data comparator configured to calculate a number of differences between values of the first data stored in the second buffer and corresponding values of the second data stored in the third buffer, and to generate the difference value.