Process window optimizer

• US 9,990,451 B2
• Filed: 02/09/2015
• Issued: 06/05/2018
• Est. Priority Date: 02/12/2014
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: ASML Netherlands BV (ASML Holding NV)
• Inventors: Hunsche, Stefan, Vellanki, Venu
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US14/616,905
• Publication Number:
  US 20150227654A1
• Time in Patent Office: 1,212 Days
• Field of Search: 716 54
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70525 Controlling normal operating mode, e.g. matching different apparatus, remote control or prediction of failure
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

Disclosed herein is a computer-implemented defect prediction method for a device manufacturing process involving processing a pattern onto a substrate, the method comprising: identifying a processing window limiting pattern (PWLP) from the pattern; determining a processing parameter under which the PWLP is processed; and determining or predicting, using the processing parameter, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the PWLP with the device manufacturing process.

Claims

1. A defect determination or prediction method for a device manufacturing process involving processing a pattern onto a substrate, the method comprising:

identifying a processing window limiting pattern from the pattern;

obtaining a measured value of a processing parameter under which the processing window limiting pattern is processed; and

determining or predicting, using the measured value of the processing parameter, or a value derived therefrom, and using a hardware-computer, an existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the processing window limiting pattern with the device manufacturing process.

2. The method of claim 1, wherein the determining or predicting the existence, the probability of existence, the characteristic, or the combination thereof, further uses a characteristic of the processing window limiting pattern, a characteristic of the pattern, or both.

3. The method of claim 1, further comprising adjusting, in the device manufacturing process, the processing parameter using the existence, the probability of existence, the characteristic, or the combination thereof, of the defect.

4. The method of claim 3, further comprising determining or predicting, using the adjusted processing parameter, an existence, probability of existence, a characteristic, or a combination thereof, of a residue defect produced from the processing window limiting pattern using the device manufacturing process.

5. The method of claim 4, further comprising indicating which one or more of a plurality of processing window limiting patterns to inspect at least partially based on the determined or predicted existence, probability of existence, the characteristic, or the combination thereof, of the residue defect.

6. The method of claim 1, further comprising determining a process window of the processing window limiting pattern.

7. The method of claim 6, wherein the determining or predicting the existence, the probability of existence, the characteristic, or the combination thereof, of the defect comprises comparing the measured value of the processing parameter, or the derived value therefrom, with the process window.

8. The method of claim 1, further comprising compiling the measured value of the processing parameter, or the derived value therefrom, into a processing parameter map.

9. The method of claim 1, wherein the processing window limiting pattern is identified using an empirical model or a computational model.

10. The method of claim 1, wherein the processing parameter is any one or more selected from:

focus, dose, a source parameter, a projection optics parameter, a characteristics of a resist used on the substrate, a characteristic of development and post-exposure baking of a resist used on the substrate, and/or a characteristic of etching of a layer of the substrate.

11. The method of claim 1, wherein the determining or predicting the existence, the probability of existence, the characteristic, or the combination thereof, of the defect comprises simulating an image or expected patterning contours of the processing window limiting pattern under the processing parameter and determining an image or contour parameter.

12. A method of manufacturing a device using a device manufacturing process involving processing a pattern onto a substrate, the method comprising:

obtaining a measured value of a processing parameter under which a previously identified processing window limiting pattern is processed;

determining or predicting, using the measured value of the processing parameter, or a value derived therefrom, an existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the processing window limiting pattern with the device manufacturing process; and

indicating which one or more of a plurality of processing window limiting patterns to inspect at least partially based on the determined or predicted existence, probability of existence, characteristic, or the combination thereof, of the defect.

13. The method of claim 12, further comprising adjusting, in the device manufacturing process, the processing parameter using the existence, the probability of existence, the characteristic, or the combination thereof, of the defect.

14. The method of claim 13, further comprising determining or predicting, using the adjusted processing parameter, an existence, probability of existence, a characteristic, or a combination thereof, of a residue defect produced from the processing window limiting pattern using the device manufacturing process.

15. The method of claim 12, further comprising inspecting, with an inspection apparatus, one or more substrates processed with the indicated one or more processing window limiting patterns.

16. A computer program product comprising a non-transitory computer readable medium having instructions recorded thereon, the instructions, when executed, are configured to cause a computer to at least:

identify a processing window limiting pattern from the pattern;

obtain a measured value of a processing parameter under which the processing window limiting pattern is processed; and

determine or predict, using the measured value of the processing parameter, or a value derived therefrom, an existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the processing window limiting pattern with the device manufacturing process.

17. The computer program product of claim 16, wherein the instructions configured to cause determination or prediction of the existence, the probability of existence, the characteristic, or the combination thereof, of defect further use a characteristic of the processing window limiting pattern, a characteristic of the pattern, or both.

18. The computer program product of claim 16, further comprising instructions configured to provide information to enable adjustment, in the device manufacturing process, of the processing parameter using the existence, the probability of existence, the characteristic, or the combination thereof, of the defect.

19. The computer program product of claim 16, further comprising instructions configured to determine or predict, using a value of an adjusted processing parameter in the device manufacturing process, an existence, probability of existence, a characteristic, or a combination thereof, of a residue defect produced from the processing window limiting pattern using the device manufacturing process.

20. The computer program product of claim 16, further comprising instructions configured to determine a process window of the processing window limiting pattern and further comprising instructions configured to compare the measured value of the processing parameter, or the derived value therefrom, with the process window to determine or predict the existence, the probability of existence, the characteristic, or the combination thereof, of the defect.