Memory control circuit unit, memory storage device and signal receiving method
First Claim
1. A memory control circuit unit, configured to control a volatile memory, and the memory control circuit unit comprising:
- a memory controller; and
a memory interface circuit, coupled to the memory controller,wherein the memory interface circuit is configured to receive a first signal from the volatile memory,wherein the memory interface circuit is further configured to adjust a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit,wherein a central value of the voltage range is not equal to a default voltage value,wherein the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage,wherein the memory interface circuit is further configured to generate an input signal according to a voltage correspondence between the first signal and an internal reference voltage.
1 Assignment
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Accused Products
Abstract
A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.
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Citations
30 Claims
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1. A memory control circuit unit, configured to control a volatile memory, and the memory control circuit unit comprising:
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a memory controller; and a memory interface circuit, coupled to the memory controller, wherein the memory interface circuit is configured to receive a first signal from the volatile memory, wherein the memory interface circuit is further configured to adjust a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, wherein a central value of the voltage range is not equal to a default voltage value, wherein the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage, wherein the memory interface circuit is further configured to generate an input signal according to a voltage correspondence between the first signal and an internal reference voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A memory storage device, comprising:
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a connection interface unit, configured to couple to a host system; a rewritable non-volatile memory module; a volatile memory; a memory control circuit unit, coupled to the connection interface unit, the rewritable non-volatile memory module and the volatile memory, wherein the memory control circuit unit is configured to receive a first signal from the volatile memory, wherein the memory control circuit unit is further configured to adjust a voltage value of the first signal to a voltage range in response to an internal impedance of the memory control circuit unit, wherein a central value of the voltage range is not equal to a default voltage value, wherein the default voltage value is one half a sum of a voltage value of a supply voltage of the memory control circuit unit and a voltage value of a reference ground voltage, wherein the memory control circuit unit is further configured to generate an input signal according to a voltage correspondence between the first signal and an internal reference voltage. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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22. A signal receiving method for a memory storage device having a volatile memory, and the signal receiving method comprising:
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receiving a first signal from the volatile memory by a memory interface circuit; adjusting a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, wherein a central value of the voltage range is not equal to a default voltage value, wherein the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage; and generating an input signal according to a voltage correspondence between the first signal and an internal reference voltage. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30)
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Specification