Flash memory data storage device and programming method thereof

• US 9,990,996 B2
• Filed: 10/07/2016
• Issued: 06/05/2018
• Est. Priority Date: 10/23/2015
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: Hsiao, Li-Shuo
• Primary Examiner(s): Ojha, Ajay
• Application Number:
  US15/288,012
• Publication Number:
  US 20170115908A1
• Time in Patent Office: 606 Days
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/1087 Data input latches

Abstract

A data storage device includes a flash memory and a controller. The flash memory includes a memory array. The controller performs a programming operation for the flash memory. After the controller issues a program command of the programming operation to the flash memory, the controller issues a first read status command to the flash memory before a page program time of the flash memory has been reached, and the controller determines whether the programming operation is performed in the flash memory according to a first memory status provided by the flash memory.

Claims

1. A data storage device, comprising:

a flash memory, comprising a memory array; and

a controller, performing a programming operation for the flash memory,

wherein after the controller issues a program command of the programming operation to the flash memory, the controller issues a first read status command to the flash memory before a page program time of the flash memory has been reached, and before the page program time of the flash memory has been reached, the controller determines whether the programming operation is performed in the flash memory according to a first memory status, wherein the first memory status is provided by the flash memory in response to the first read status command,

wherein when the controller determines that the programming operation is being performed in the flash memory, the controller issues a second read status command to the flash memory after exceeding the page program time of the flash memory, and the controller determines whether the programming operation has succeeded according to a second memory status provided by the flash memory.

2. The data storage device as claimed in claim 1, wherein when the first memory status indicates that the flash memory is idle, the controller determines that the programming operation has not been performed in the flash memory.

3. The data storage device as claimed in claim 2, wherein when the flash memory is idle, the first memory status provided by the flash memory is E0h.

4. The data storage device as claimed in claim 1, wherein when the first memory status indicates that the flash memory is busy, the controller determines that the programming operation is being performed in the flash memory.

5. The data storage device as claimed in claim 4, wherein when the flash memory is busy, the first memory status provided by the flash memory is 80h.

6. The data storage device as claimed in claim 1, wherein when the second memory status provided by the flash memory is E0h, the controller determines that the programming operation has succeeded.

7. The data storage device as claimed in claim 1, wherein when the second memory status provided by the flash memory is E1h, the controller determines that the programming operation has failed.

8. The data storage device as claimed in claim 1, wherein before issuing the program command of the programming operation, the controller further issues a serial data input command, a program address, and program data to the flash memory.

9. The data storage device as claimed in claim 8, wherein in the programming operation, the flash memory stores the program data into the memory array according to the program address in response to the program command.