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Integrating a planar field effect transistor (FET) with a vertical FET

  • US 9,991,170 B2
  • Filed: 10/07/2016
  • Issued: 06/05/2018
  • Est. Priority Date: 12/16/2015
  • Status: Active Grant
First Claim
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1. A method comprising:

  • determining an integration scheme for integrating a planar field-effect transistor (FET) with a vertical FET, wherein the integration scheme optimizes costs and complexity; and

    manufacturing a semiconductor structure comprising the planar FET and the vertical FET by integrating the planar FET with the vertical FET based on the integration scheme;

    wherein the vertical FET comprises a first semiconductor and a vertical gate perpendicular to and extending across the first semiconductor;

    wherein the planar FET comprises a second semiconductor and a planar gate perpendicular to and extending across the second semiconductor; and

    wherein a top of the vertical gate and a top of the planar gate are co-planar.

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