HVMOS reliability evaluation using bulk resistances as indices

• US 9,991,260 B2
• Filed: 12/04/2015
• Issued: 06/05/2018
• Est. Priority Date: 05/19/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Chi-Feng, Chen, Chia-Chung, Lu, Tse-Hua
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): Klein, Jordan
• Application Number:
  US14/959,393
• Publication Number:
  US 20160086948A1
• Time in Patent Office: 914 Days
• Field of Search: None
• CPC Class Codes: G01R 27/08 Measuring resistance by measuring both voltage and current
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.

Claims

1. A semiconductor chip comprising:

a plurality of High-Voltage P-type Metal-Oxide-Semiconductor (HVPMOS) devices; and

at least one n-type guard ring adjacent to the plurality of HVPMOS devices, wherein all HVPMOS devices in the semiconductor chip and having adjacent guard rings have active-region-to-guard-ring spacings smaller than about 2 μ

m, wherein the active-region-to-guard-ring spacings are distances between outer edges of active regions of the respective HVPMOS devices and corresponding nearest n-type guard rings, and wherein the active-region-to-guard-ring spacings are measured in channel width directions of the respective HVPMOS devices.

2. The semiconductor chip of claim 1, wherein the plurality of HVPMOS devices forms a row, with no High-Voltage N-type Metal-Oxide-Semiconductor (HVNMOS) device between the plurality of HVPMOS devices.

3. The semiconductor chip of claim 2, wherein the plurality of HVPMOS devices is encircled by a same n-type guard ring, and wherein the plurality of HVPMOS devices is spaced apart from each other by Shallow Trench Isolation (STI) regions.

4. The semiconductor chip of claim 3, wherein no guard ring separates the plurality of HVPMOS devices from each other.

5. The semiconductor chip of claim 2, wherein the plurality of HVPMOS devices is encircled by a same adjacent n-type guard ring, and forms an array, and wherein the plurality of HVPMOS devices is spaced apart from each other by Shallow Trench Isolation (STI) regions.

6. The semiconductor chip of claim 2, the plurality of HVPMOS devices forms an array, and wherein the plurality of HVPMOS devices is spaced apart from each other by a plurality of guard rings.

7. The semiconductor chip of claim 1, wherein the all HVPMOS devices comprise a digital HVPMOS device and a radio-frequency HVPMOS device.

8. The semiconductor chip of claim 1 further comprising:

a High-Voltage N-type Metal-Oxide-Semiconductor (HVNMOS) device; and

an additional n-type guard ring encircling the HVNMOS device, wherein an additional active-region-to-guard-ring spacing of the HVNMOS device from the additional n-type guard ring is greater than 50 μ

m.

9. A semiconductor chip comprising:

a semiconductor substrate;

a plurality of High-Voltage P-type Metal-Oxide-Semiconductor (HVPMOS) devices at a surface of the semiconductor substrate, wherein the plurality of HVPMOS devices forms an array comprising a plurality of rows and a plurality of columns; and

an n-type guard ring encircling the plurality of HVPMOS devices, with no High-Voltage N-type Metal-Oxide-Semiconductor (HVNMOS) devices encircled by the n-type guard ring.

10. The semiconductor chip of claim 9, wherein each of the plurality of HVPMOS devices comprises an active region fully encircled by a portion of a shallow trench isolation region.

11. The semiconductor chip of claim 10, wherein the active region of the each of the plurality of HVPMOS devices has an active-region-to-guard-ring spacing smaller than about 2 μ

m, and wherein the active-region-to-guard-ring spacing is between the active region and a nearest portion of the n-type guard ring.

12. The semiconductor chip of claim 9, wherein active regions of neighboring ones of the plurality of HVPMOS devices in a same column has an active-region-spacing smaller than about 6 μ

m.

13. The semiconductor chip of claim 9, wherein a region encircled by the n-type guard ring has a length and a width smaller than a length, with the width being smaller than about 30 μ

m.

14. The semiconductor chip of claim 13, wherein the width is measured in a direction perpendicular to lengthwise directions of active regions of the plurality of HVPMOS devices.

15. A semiconductor chip comprising:

a semiconductor substrate;

a first plurality of High-Voltage P-type Metal-Oxide-Semiconductor (HVPMOS) devices formed at a surface of the semiconductor substrate, wherein the first plurality of HVPMOS devices forms a row;

an isolation region extending into the semiconductor substrate, wherein the isolation region isolates each of the first plurality of HVPMOS devices from other; and

an n-type guard ring encircling the isolation region.

16. The semiconductor chip of claim 15, wherein no High-Voltage N-type Metal-Oxide-Semiconductor (HVNMOS) device is encircled by the n-type guard ring.

17. The semiconductor chip of claim 16, wherein each of the first plurality of HVPMOS devices comprises an active region fully encircled by the isolation region.

18. The semiconductor chip of claim 17, wherein the active region of the each of the first plurality of HVPMOS devices has an active-region-to-guard-ring spacing smaller than about 2 μ

m, and the active-region-to-guard-ring spacing is between the active region and a nearest portion of the n-type guard ring.

19. The semiconductor chip of claim 15, wherein a region encircled by the n-type guard ring has a length and a width smaller than a length, with the width being smaller than about 30 μ

m, wherein the width is measured in a direction perpendicular to lengthwise directions of active regions of the first plurality of HVPMOS devices.

20. The semiconductor chip of claim 15 further comprising a second plurality of HVPMOS devices, wherein the first plurality of HVPMOS devices and the second plurality of HVPMOS devices in combination form an array comprising a plurality of rows and a plurality of columns, and wherein the isolation region isolates each of the first plurality of HVPMOS devices and the second plurality of HVPMOS devices from each other.