Semiconductor device and method for manufacturing the same

• US 9,991,288 B2
• Filed: 06/12/2017
• Issued: 06/05/2018
• Est. Priority Date: 02/05/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US15/619,650
• Publication Number:
  US 20170278875A1
• Time in Patent Office: 358 Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

Claims

1. A semiconductor device comprising:

a first insulating layer;

a first oxide semiconductor layer over the first insulating layer;

a second oxide semiconductor layer over the first insulating layer;

a second insulating layer over the first oxide semiconductor layer and the second oxide semiconductor layer;

a source electrode layer electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer;

a drain electrode layer electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer;

a pair of first gate electrode layers interposing the first oxide semiconductor layer; and

a pair of second gate electrode layers interposing the second oxide semiconductor layer,

wherein the pair of first gate electrode layers is electrically connected to the pair of second gate electrode layers,

wherein the pair of first gate electrode layers extends beyond both side edges of the first oxide semiconductor layer in a channel width direction of the first oxide semiconductor layer,

wherein the pair of second gate electrode layers extends beyond both side edges of the second oxide semiconductor layer in a channel width direction of the second oxide semiconductor layer,

wherein a channel width of the first oxide semiconductor layer is larger than a channel length of the first oxide semiconductor layer,

wherein a channel width of the second oxide semiconductor layer is larger than a channel length of the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the second oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the first oxide semiconductor layer comprises a crystal region which is c-axis-aligned perpendicularly to a surface of the first oxide semiconductor layer, and

wherein the second oxide semiconductor layer comprises a crystal region which is c-axis-aligned perpendicularly to a surface of the second oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer comprises a stack of a first film and a second film.

3. The semiconductor device according to claim 1, further comprising:

a third insulating layer over the second insulating layer,

wherein the second insulating layer comprises oxygen and silicon, and

wherein the third insulating layer comprises nitrogen and silicon.

4. A semiconductor device comprising:

a first insulating layer;

a first oxide semiconductor layer over the first insulating layer;

a second oxide semiconductor layer over the first insulating layer;

a second insulating layer over the first oxide semiconductor layer and the second oxide semiconductor layer;

a source electrode layer electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer;

a drain electrode layer electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer;

a first gate electrode layer overlapping with the first oxide semiconductor layer; and

a second gate electrode layer overlapping with the second oxide semiconductor layer,

wherein the first gate electrode layer is electrically connected to the second gate electrode layer,

wherein the first gate electrode layer extends beyond both side edges of the first oxide semiconductor layer in a channel width direction of the first oxide semiconductor layer,

wherein the second gate electrode layer extends beyond both side edges of the second oxide semiconductor layer in a channel width direction of the second oxide semiconductor layer,

wherein a channel width of the first oxide semiconductor layer is larger than a channel length of the first oxide semiconductor layer,

wherein a channel width of the second oxide semiconductor layer is larger than a channel length of the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the second oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the first oxide semiconductor layer comprises a crystal region which is c-axis-aligned perpendicularly to a surface of the first oxide semiconductor layer, and

wherein the second oxide semiconductor layer comprises a crystal region which is c-axis-aligned perpendicularly to a surface of the second oxide semiconductor layer.

5. The semiconductor device according to claim 4, wherein the first oxide semiconductor layer comprises a stack of a first film and a second film.

6. The semiconductor device according to claim 4, further comprising:

a third insulating layer over the second insulating layer,

wherein the second insulating layer comprises oxygen and silicon, and

wherein the third insulating layer comprises nitrogen and silicon.

7. A semiconductor device comprising:

a driver circuit comprising;

a first insulating layer;

a first oxide semiconductor layer over the first insulating layer;

a second oxide semiconductor layer over the first insulating layer;

a second insulating layer over the first oxide semiconductor layer and the second oxide semiconductor layer;

a source electrode layer electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer;

a drain electrode layer electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer;

a first gate electrode layer overlapping with the first oxide semiconductor layer; and

a second gate electrode layer overlapping with the second oxide semiconductor layer,

wherein the first gate electrode layer is electrically connected to the second gate electrode layer,

wherein the first gate electrode layer extends beyond both side edges of the first oxide semiconductor layer in, a channel width direction of the first oxide semiconductor layer,

wherein the second gate electrode layer extends beyond both side edges of the second oxide semiconductor layer in a channel width direction of the second oxide semiconductor layer,

wherein a channel width of the first oxide semiconductor layer is larger than a channel length of the first oxide semiconductor layer,

wherein a channel, width of the second oxide semiconductor layer is larger than a channel length of the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the second oxide semiconductor layer comprises indium, gallium, and zinc,

wherein the first oxide semiconductor layer comprises a crystal region which is c-axis-aligned perpendicularly to a surface of the first oxide semiconductor layer,

wherein the second oxide semiconductor layer comprises a crystal region which is c-axis-aligned perpendicularly to a surface of the second oxide semiconductor layer, and

wherein the first oxide semiconductor layer comprises a stack of a first film and a second film.

8. The semiconductor device according to claim 7, further comprising:

a third insulating layer over the second insulating layer,

wherein the second insulating layer comprises oxygen and silicon, and

wherein the third insulating layer comprises nitrogen and silicon.