Pixel structure having a single side overlapping light shielding pattern

• US 9,991,289 B2
• Filed: 03/29/2017
• Issued: 06/05/2018
• Est. Priority Date: 07/23/2015
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: I, Chu-Hsuan, Chen, Yi-Wei
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US15/472,280
• Publication Number:
  US 20170200741A1
• Time in Patent Office: 433 Days
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs

Abstract

An active device of a pixel structure includes a semiconductor layer, an insulation layer covering the semiconductor layer, a gate electrode disposed on the insulation layer and electrically connected to a scan line, a protection layer covering the gate electrode, a source electrode and a drain electrode electrically connected to a source region and a drain region of the semiconductor layer. A channel region is disposed between the source region and the drain region. A source lightly doped region is disposed between the channel region and the source region. A drain lightly doped region is disposed between the channel region and the drain region. The light shielding pattern shields the source lightly doped region and the drain lightly doped region. The light shielding pattern is overlapped with one side of the scan line and not overlapped with another side of the scan line.

Claims

1. A pixel structure, comprising:

a scan line and a data line intersecting each other;

an active device, electrically connected to the scan line and the data line, wherein the active device comprises;

a semiconductor layer, comprising a source region, a drain region, a channel region, a source lightly doped region, and a drain lightly doped region, wherein the channel region is located between the source region and the drain region, the source lightly doped region is located between the channel region and the source region, and the drain lightly doped region is located between the channel region and the drain region;

an insulating layer, covering the semiconductor layer;

a gate electrode, located on the insulating layer above the channel region and electrically connected to the scan line;

a protection layer, covering the gate electrode; and

a source electrode and a drain electrode, located on the protection layer and respectively electrically connected to the source region and the drain region, wherein the source electrode is electrically connected to the data line;

a pixel electrode, electrically connected to the drain electrode; and

a light shielding pattern, substantially shielding the source lightly doped region and the drain lightly doped region of the semiconductor layer, wherein the light shielding pattern is overlapped with a side of the scan line and not overlapped with another side of the scan line.

2. The pixel structure as claimed in claim 1, wherein there is an overlapped region between the light shielding pattern and the scan line, and a width of the overlapped region is in a range from 50% to 100% of a width of the scan line.

3. The pixel structure as claimed in claim 1, wherein the light shielding layer is located below the semiconductor layer, and a buffer layer is further disposed between the light shielding layer and the semiconductor layer.

4. The pixel structure as claimed in claim 1, wherein:

the semiconductor layer further comprises a connection region and a lightly doped region, and the channel region of the semiconductor layer further comprises a first channel region and a second channel region, wherein the connection region is located between the first channel region and the second channel region, the lightly doped region is located between the connection region and the first channel region and between the connection region and the second channel region, the source lightly doped region is located between the source region and the first channel region, and the drain lightly doped region is located between the drain region and the second channel region; and

the gate electrode comprises a first gate electrode and a second gate electrode respectively located above the first channel region and the second channel region, wherein the first gate electrode and the second gate electrode are connected to each other.

5. The pixel structure as claimed in claim 4, wherein the light shielding pattern does not shield the connection region and the lightly doped region.

6. The pixel structure as claimed in claim 4, wherein the light shielding pattern shields a portion of the first channel region and a portion of the second channel region.

7. The pixel structure as claimed in claim 1, wherein the source electrode and the drain electrode are respectively located at two sides of the scan line.

8. The pixel structure as claimed in claim 7, further comprising a black matrix layer, wherein the black matrix layer comprises a first light blocking portion and a second light blocking portion respectively parallel to the scan line and the data line, and the first light blocking portion of the black matrix layer substantially shields the drain electrode but does not shield the source electrode.

9. The pixel structure as claimed in claim 7, wherein the semiconductor layer is an L-shaped pattern, and the source electrode and the drain electrode are respectively and correspondingly disposed at two ends of the semiconductor layer in the L-shaped pattern.

10. The pixel structure as claimed in claim 1, wherein the source electrode and the drain electrode are located at the same side of the scan line.

11. The pixel structure as claimed in claim 10, further comprising a black matrix layer disposed in correspondence with the scan line and the data line, wherein the black matrix layer substantially shields the drain electrode but does not shield the source electrode.

12. The pixel structure as claimed in claim 10, wherein the semiconductor layer is in a U-shaped pattern, the source electrode and the drain electrode are respectively and correspondingly disposed at two ends of the semiconductor layer in the U-shaped pattern, and a bent portion of the semiconductor layer in the U-shaped pattern is located at another side of the scan line.

13. The pixel structure as claimed in claim 12, further comprising a black matrix layer, wherein the black matrix layer comprises a first light blocking portion and a second light blocking portion respectively parallel to the scan line and the data line, the first light blocking portion of the black matrix layer substantially shields the drain electrode but does not shield the source electrode, and the first light blocking portion of the black matrix layer is not overlapped with the bent portion of the semiconductor layer.

14. The pixel structure as claimed in claim 1, further comprising a common electrode disposed in correspondence with the pixel electrode.