Semiconductor device and manufacturing method thereof

• US 9,991,293 B2
• Filed: 09/02/2014
• Issued: 06/05/2018
• Est. Priority Date: 11/25/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun
• Primary Examiner(s): NGUYEN, SOPHIA T
• Application Number:
  US14/474,370
• Publication Number:
  US 20140370654A1
• Time in Patent Office: 1,372 Days
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/13625 Patterning using multi-mask exposure
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/1315 comprising structures specially adapted for lowering the resistance

Abstract

A step for forming an island-shaped semiconductor layer of a semiconductor device used in a display device is omitted in order to manufacture the semiconductor device with high productivity and low cost. The semiconductor device is manufactured through four photolithography processes: four steps for forming a gate electrode, for forming a source electrode and a drain electrode, for forming a contact hole, and for forming a pixel electrode. In the step for forming the contact hole, a groove portion in which a semiconductor layer is removed is formed, whereby formation of a parasitic transistor is prevented. An oxide semiconductor is used as a material of the semiconductor layer in which a channel is formed, and an oxide semiconductor having a higher insulating property than the semiconductor layer is provided over the semiconductor layer.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode, a first wiring and a capacitor wiring over a substrate by a first photolithography process;

forming a gate insulating layer over the gate electrode;

forming a first semiconductor layer including a first oxide semiconductor over the gate insulating layer;

forming a source electrode, a drain electrode, and a second wiring over the first semiconductor layer by a second photolithography process;

performing a cleaning treatment using a solution of diluted hydrofluoric acid after the step of forming the source electrode and the drain electrode so that at least a part of impurities attached to a surface of the first semiconductor layer is removed, wherein the solution of diluted hydrofluoric acid has a concentration of 0.5 wt % to 5×

10-4 wt %;

forming a second semiconductor layer including a second oxide semiconductor having a higher insulating property than the first semiconductor layer over the source electrode and the drain electrode after the step of performing the cleaning treatment;

forming a contact hole by selectively removing a portion of the second semiconductor layer that overlaps with the drain electrode and forming a groove portion by removing a portion of the second semiconductor layer, the first semiconductor layer, and the gate insulating layer, by a third photolithography process; and

forming a pixel electrode over the second semiconductor layer and an electrode over the drain electrode by a fourth photolithography process,

wherein the first wiring is electrically connected to the gate electrode,

wherein the second wiring is electrically connected to the source electrode, the pixel electrode, and the capacitor wiring, and

wherein the electrode is in direct contact with a side surface of the first semiconductor layer and a side surface of the gate electrode.

2. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode, a first wiring and a capacitor wiring over a substrate;

forming a gate insulating layer over the gate electrode;

forming a first semiconductor layer including a first oxide semiconductor over the gate insulating layer;

forming a source electrode, a drain electrode, and a second wiring over the first semiconductor layer;

performing a cleaning treatment using a solution of diluted hydrofluoric acid after the step of forming the source electrode and the drain electrode so that at least a part of impurities attached to a surface of the first semiconductor layer is removed, wherein the solution of diluted hydrofluoric acid has a concentration of 0.5 wt % to 5×

10-4 wt %;

forming a second semiconductor layer including a second oxide semiconductor having a higher insulating property than the first semiconductor layer over the source electrode and the drain electrode after the step of performing the cleaning treatment;

forming a contact hole by selectively removing a portion of the second semiconductor layer that overlaps with the drain electrode and forming a groove portion by removing a portion of the second semiconductor layer, the first semiconductor layer, and the gate insulating layer; and

forming a pixel electrode over the second semiconductor layer and an electrode over the drain electrode,

wherein the first wiring is electrically connected to the gate electrode,

wherein the second wiring is electrically connected to the source electrode,

wherein the first semiconductor layer overlaps with the first wiring, the second wiring, the pixel electrode, and the capacitor wiring, and

wherein the electrode is in direct contact with a side surface of the first semiconductor layer and a side surface of the gate electrode.

3. The method for manufacturing the semiconductor device according to claim 1, wherein the second semiconductor layer is formed to include oxygen that exceeds the stoichiometric composition.

4. The method for manufacturing the semiconductor device according to claim 2, wherein the second semiconductor layer is formed to include oxygen that exceeds the stoichiometric composition.

5. The method for manufacturing the semiconductor device according to claim 1,

wherein the source electrode and the drain electrode is in direct contact with the first semiconductor layer,

wherein the second semiconductor layer is in direct contact with the source electrode and the drain electrode,

wherein the first oxide semiconductor contains indium, gallium and zinc, and

wherein the second oxide semiconductor contains indium, yttrium and zinc.

6. The method for manufacturing the semiconductor device according to claim 2,

wherein the source electrode and the drain electrode is in direct contact with the first semiconductor layer,

wherein the second semiconductor layer is in direct contact with the source electrode and the drain electrode,

wherein the first oxide semiconductor contains indium, gallium and zinc, and

wherein the second oxide semiconductor contains indium, zirconium and zinc.