Buried channel deeply depleted channel transistor

• US 9,991,300 B2
• Filed: 07/25/2017
• Issued: 06/05/2018
• Est. Priority Date: 05/24/2013
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Bakhishev, Teymur, Wang, Lingquan, Zhao, Dalong, Ranade, Pushkar, Thompson, Scott E.
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US15/658,907
• Publication Number:
  US 20170323916A1
• Time in Patent Office: 315 Days
• Field of Search: None
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a first device region and a second device region of a first conductivity type;

a first source region and a first drain region of a second conductivity type formed in the first device region;

a second source region and a second drain region of a second conductivity type formed in the second device region;

a channel region of the second conductivity type formed in the first device region between the first source region and the first drain region;

an un-doped channel region in the second device region between the second source region and the second drain region; and

a first screening region of the first conductivity type formed in the first device region below the channel region and between the first source region and the first drain region, a doping density of the first screening region being higher than a doping density of the first device region;

a second screening region of the first conductivity type formed in the second device region below the un-doped channel region and between the second source region and the second drain region, a doping density of the second screening region being higher than a doping density of the second device region; and

a first gate structure formed on the first device region,

a second gate structure formed on the second device region wherein the channel region is modified, in response to a bias voltage at the first gate structure, to provide current flow from the first drain region to the first source region; and

the un-doped channel region is modified, in response to a bias voltage at the second gate structure, to provide current flow from the second drain region to the second source region.

2. The semiconductor of claim 1 wherein the channel region has an effective doping density of the second conductivity type less than an effective doping density of the second conductivity type for the first source region and the first drain region and less than an effective doping density of the first conductivity type for the first screening region.