Semiconductor device having a polarization super junction field effect transistor, electric equipment, bidirectional field effect transistor, and mounted structure body having the same

• US 9,991,335 B2
• Filed: 11/18/2014
• Issued: 06/05/2018
• Est. Priority Date: 04/18/2014
• Status: Active Grant

• Current Assignee: Powdec K.K.
• Original Assignee: Powdec K.K.
• Inventors: Echigoya, Shoko, Nakamura, Fumihiko, Yagi, Shuichi, Matsumoto, Souta, Kawai, Hiroji
• Primary Examiner(s): Ho, Anthony
• Assistant Examiner(s): Hoque, Mohammad M
• Application Number:
  US14/890,659
• Publication Number:
  US 20160093691A1
• Time in Patent Office: 1,295 Days
• Field of Search: 257 76
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage resistance and high speed in the semiconductor device using a polarization super junction, realize both the high voltage resistance and elimination of the occurrence of current collapse, operate at a high speed, and further the loss is low. The semiconductor device comprises a polarization super junction region and a p-electrode contact region. The polarization super junction region comprises an undoped GaN layer 11, an undoped Al_xGa_1-xN layer 12 with a thickness not smaller than 25 nm and not larger than 47 nm and 0.17≤x≤0.35, an undoped GaN layer 13 and a p-type GaN layer 14. When the reduced thickness tR is defined as tR=u+v(1+w×10⁻¹⁸) for the thickness u [nm] of the undoped GaN layer 13, the thickness v [nm] and the Mg concentration w [cm⁻³] of the p-type GaN layer 14, tR≥0.864/(x−0.134)+46.0 [nm] is satisfied. The p-electrode contact region comprises a p-type GaN contact layer formed to be in contact with the p-type GaN layer 14 and a p-electrode that is in contact with the p-type GaN contact layer.

Claims

1. A semiconductor device, comprising:

a polarization super junction region and a p-electrode contact region which are separated from each other,

the polarization super junction region, comprising;

a first undoped GaN layer,

an undoped Al_xGa_1-xN layer (0.17≤

x≤

0.35) with a thickness not smaller than 25 nm and not larger than 47 nm on the first undoped GaN layer,

a second undoped GaN layer on the undoped layer; and

a Mg-doped p-type GaN layer on the second undoped GaN layer,

tR≥

0.864/(x−

0.134)+46.0 [nm]

being satisfied when the thickness of the second undoped GaN layer is denoted as u[nm], the thickness of the p-type GaN layer is denoted as v[nm], the Mg concentration of the p-type GaN layer is denoted as w [cm<sup>−

3</sup>] and the reduced thickness tR is defined as

tR=u+v(1+w×

10<sup>−

18</sup>),

wherein the thickness of the p-type GaN layer v [nm]≤

20 [nm] and the Mg concentration of the p-type GaN layer w[cm<sup>−

3</sup>]≤

5×

10¹⁸[cm<sup>−

3</sup>],

the p-electrode contact region, comprising;

a p-type GaN contact layer which is doped with Mg heavier than the p-type GaN layer, provided in contact with the p-type GaN layer only in the p-electrode contact region; and

a p-electrode which is in ohmic contact with the p-type GaN contact layer,

a two-dimensional hole gas being formed in the second undoped GaN layer in the vicinity part of a hetero-interface between the undoped Al_xGa_1-xN layer and the second undoped GaN layer, and a two-dimensional electron gas being formed in the first undoped GaN layer in the vicinity part of a hetero-interface between the first undoped GaN layer and the undoped Al_xGa_1-xN layer at a non-operating time.

2. The semiconductor device according to claim 1 wherein the p-type GaN contact layer is formed on the p-type GaN layer as a mesa.

3. The semiconductor device according to claim 2 wherein the semiconductor device is a field effect transistor, and the second undoped GaN layer and the p-type GaN layer on the undoped Al_xGa_1-xN layer are patterned as a mesa, the p-type GaN contact layer is formed on the p-type GaN layer as a mesa, a source electrode and a drain electrode are formed on the undoped Al_xGa_1-xN layer so as to sandwich the second undoped GaN layer and the p-type GaN layer, and the p-electrode serving also as a gate electrode is formed on the p-type GaN contact layer.