Trench power semiconductor device
First Claim
1. A trench power semiconductor device comprising:
- a substrate;
an epitaxial layer formed on the substrate, wherein the epitaxial layer has at least one cell trench formed therein; and
a trench gate structure arranged in the cell trench, wherein the trench gate structure comprises;
a shielding electrode arranged in the cell trench;
a first dielectric layer formed in the cell trench and having a contour substantially similar to that of an inner wall surface of the cell trench, wherein the first dielectric layer has a first upper inner wall and a lower inner wall connected to the first upper inner wall;
a second dielectric layer covering the lower inner wall, wherein the second dielectric layer is made from a different material than the first dielectric layer;
a gate electrode arranged in the cell trench, wherein the gate electrode includes a first conductive layer covering the first upper inner wall, and the first conductive layer has a bottom end connected to a first ending surface of the second dielectric layer; and
a third dielectric layer conformingly covering inner surfaces of the first conductive layer and the second dielectric layer, wherein the third dielectric layer surrounds the shielding electrode so as to isolate the shielding electrode from the gate electrode;
wherein a vertical central line of the first conductive layer is spaced apart away from a vertical central line of the shielding electrode.
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Accused Products
Abstract
A trench power semiconductor device is provided. A trench gate structure of the trench power semiconductor device located in a cell trench of an epitaxial layer includes a first dielectric layer, a second dielectric layer, a gate electrode, a third dielectric layer, and a shielding layer. The second dielectric layer is interposed between the first and third dielectric layers, and the second dielectric layer is made from different material than the first dielectric layer. After performing a selective etching step on the second dielectric layer, a recess can be formed among the first, second and third dielectric layers. The gate electrode includes a conductive layer formed in the recess region, and the shielding electrode is surrounded by the third dielectric layer and insulated from the conductive layer.
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Citations
19 Claims
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1. A trench power semiconductor device comprising:
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a substrate; an epitaxial layer formed on the substrate, wherein the epitaxial layer has at least one cell trench formed therein; and a trench gate structure arranged in the cell trench, wherein the trench gate structure comprises; a shielding electrode arranged in the cell trench; a first dielectric layer formed in the cell trench and having a contour substantially similar to that of an inner wall surface of the cell trench, wherein the first dielectric layer has a first upper inner wall and a lower inner wall connected to the first upper inner wall; a second dielectric layer covering the lower inner wall, wherein the second dielectric layer is made from a different material than the first dielectric layer; a gate electrode arranged in the cell trench, wherein the gate electrode includes a first conductive layer covering the first upper inner wall, and the first conductive layer has a bottom end connected to a first ending surface of the second dielectric layer; and a third dielectric layer conformingly covering inner surfaces of the first conductive layer and the second dielectric layer, wherein the third dielectric layer surrounds the shielding electrode so as to isolate the shielding electrode from the gate electrode; wherein a vertical central line of the first conductive layer is spaced apart away from a vertical central line of the shielding electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A trench power semiconductor device comprising:
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a substrate; an epitaxial layer disposed on the substrate and having at least one cell trench and at least one termination trench formed therein; a trench gate structure is arranged in the cell trench; and a terminal electrode structure arranged in the termination trench, wherein the terminal electrode structure includes; a terminal dielectric layer having a contour substantially similar to a contour of an inner wall surface of the termination trench, wherein the terminal dielectric layer includes a first insulating layer, a second insulating layer and a third insulating layer sequentially stacked on the inner wall surface of the termination trench, the second insulating layer is made from a different material than the third insulating layer, and an end face of the second insulating layer is located lower than a top surface of the first insulating layer and a top surface of the third insulating layer to define a recess among the first, second, and third insulating layers; a conductive layer arranged in the recess, wherein the conductive layer is connected to one of the two end surfaces of the second insulating layer, which is closer to the trench gate structure; and a terminal electrode arranged in the termination trench and isolated from the conductive layer by the third insulating layer. - View Dependent Claims (15, 16, 17, 18)
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19. A trench power semiconductor device comprising:
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a substrate; an epitaxial layer formed on the substrate, wherein the epitaxial layer has at least one cell trench formed therein; and a trench gate structure arranged in the cell trench, wherein the trench gate structure comprises; a shielding electrode arranged in the cell trench; a first dielectric layer formed in the cell trench and having a contour substantially similar to that of an inner wall surface of the cell trench, wherein the first dielectric layer has a first upper inner wall and a lower inner wall connected to the first upper inner wall; a second dielectric layer covering the lower inner wall, wherein the second dielectric layer is made from a different material than the first dielectric layer; a gate electrode arranged in the cell trench, wherein the gate electrode includes a first conductive layer covering the first upper inner wall, and the first conductive layer has a bottom end connected to a first ending surface of the second dielectric layer; and a third dielectric layer conformingly covering inner surfaces of the first conductive layer and the second dielectric layer, wherein the third dielectric layer surrounds the shielding electrode so as to isolate the shielding electrode from the gate electrode; wherein the entire thickness of the first conductive layer in a direction parallel to a surface of the epitaxial layer and the entire thickness of the second dielectric layer in a direction parallel to the surface of the epitaxial layer both range from 200 nm to 250 nm.
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Specification