Power factor correction circuit for regulating operating frequency control circuit of power factor correction circuit and control method thereof, electronic apparatus, and power adapter

• US 9,991,788 B2
• Filed: 12/22/2016
• Issued: 06/05/2018
• Est. Priority Date: 12/25/2015
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Oe, Takumi, Murakami, Hiroyuki
• Primary Examiner(s): Gblende, Jeffrey
• Assistant Examiner(s): SINGH, DAVID ANTHONY
• Application Number:
  US15/388,251
• Publication Number:
  US 20170187279A1
• Time in Patent Office: 530 Days
• CPC Class Codes: H02M 1/42 Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1586 switched with a phase shift, i.e. interleaved
• CPC Class Codes: H02M 7/06 using discharge tubes without control electrode or semiconductor devices without control electrode
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A control circuit of a power factor correction circuit including two channels, each of which includes a switching transistor, an inductor and a rectification element, includes: an error amplifier amplifying an error of a feedback signal according to output voltage of the power factor correction circuit and target value of the feedback signal and generating an error signal; a pulse modulator generating first and second pulse modulated signals in current critical mode in response to the error signal; a first driver driving the switching transistor of first channel based on the first pulse modulated signal; and a second driver driving the switching transistor of second channel based on the second pulse modulated signal, wherein the pulse modulator switches between a first mode where phase difference between the first and second pulse modulated signals is 180° and a second mode where the first and second channels are exclusively and alternately used.

Claims

1. A control circuit of a power factor correction circuit constituted by two channels, each of which includes a switching transistor, an inductor and a rectification element, comprising:

an error amplifier configured to amplify an error of a feedback signal according to an output voltage of the power factor correction circuit and a target value of the feedback signal and generate an error signal;

a pulse modulator configured to generate a first pulse modulated signal and a second pulse modulated signal in a current critical mode in response to the error signal;

a first driver configured to drive the switching transistor of a first channel based on the first pulse modulated signal;

a second driver configured to drive the switching transistor of a second channel based on the second pulse modulated signal; and

a mode controller configured to monitor a total current of the first channel and the second channel and generate a mode control signal based on the total current,

wherein the pulse modulator switches between a first mode in which a phase difference between the first pulse modulated signal and the second pulse modulated signal is 180° and

a second mode in which the first channel and the second channel are exclusively and alternately used every switching period, in response to the mode control signal.

2. The control circuit of claim 1, wherein the power factor correction circuit further includes a sense resistor disposed on a path of an input current of the power factor correction circuit, and

wherein the mode controller configured to generate the mode control signal to switch between the first mode and the second mode based on a result of comparison between a voltage drop of the sense resistor and a threshold voltage.

3. The control circuit of claim 2, wherein the mode controller includes:

a resistor connection terminal to which an external first resistor is connected;

a voltage source configured to supply a reference voltage to the resistor connection terminal via a second resistor; and

a comparator configured to compare a voltage drop of the sense resistor and the threshold voltage generated in the resistor connection terminal.

4. The control circuit of claim 1, wherein the pulse modulator includes:

a first reset signal generator configured to generate a first reset signal defining an on-time of the switching transistor of the first channel based on the error signal;

a second reset signal generator configured to generate a second reset signal defining an on-time of the switching transistor of the second channel based on the error signal;

a first set signal generator configured to generate a first set signal defining an off-time of the switching transistor of the first channel;

a second set signal generator configured to generate a second set signal defining an off-time of the switching transistor of the second channel; and

a logic circuit configured to generate the first pulse modulated signal and the second pulse modulated signal based on the first set signal, the first reset signal, the second set signal and the second reset signal.

5. The control circuit of claim 1, wherein the control circuit is integrated on a single semiconductor substrate.

6. A power factor correction circuit comprising a control circuit of claim 1.

7. An electronic apparatus comprising:

a rectification circuit configured to rectify an AC voltage; and

the power factor correction circuit of claim 6 which is configured to receive an output voltage of the rectification circuit.

8. A power adapter comprising:

a rectification circuit configured to rectify an AC voltage; and

the power factor correction circuit of claim 6 which is configured to receive an output voltage of the rectification circuit.

9. A control circuit of a power factor correction circuit constituted by M (M being an integer of two or more) channels, each of which includes a switching transistor, an inductor and a rectification element, the control circuit comprising:

an error amplifier configured to amplify an error of a feedback signal according to an output voltage of the power factor correction circuit and a target value of the feedback signal and generate an error signal;

a pulse modulator configured to generate pulse modulated signals of the M channels in a current critical mode in response to the error signal;

M drivers which correspond respectively to the M channels and are configured to drive the respective corresponding switching transistors based on the respective corresponding pulse modulated signals; and

a mode controller configured to monitor a total current of the first channel and the second channel and generate a mode control signal based on the total current,

wherein the pulse modulator is further configured to switch between a first mode in which the pulse modulated signals of the M channels sequentially transition to an on-level with a phase difference of 360°

/M and a second mode in which a plurality of consecutive switching periods are set as a period group, in response to the mode control signal, and, in each switching period included in the period group, a pulse modulated signal of one channel transitions to an on-level and then an off-level and pulse modulated signals of the remaining (M−

1) channels are kept at an off-level, and, during one period group, each pulse modulated signal transitions to the off-level at least once after transitioning to the on-level.

10. The control circuit of claim 9, wherein the power factor correction circuit further includes a sense resistor disposed on a path of an input current of the power factor correction circuit, and

wherein the mode controller configured to generate the mode control signal to switch between the first mode and the second mode based on a result of comparison between a voltage drop of the sense resistor and a threshold voltage.

11. The control circuit of claim 9, wherein M=2, and the period group includes two switching periods.

12. The control circuit of claim 9, wherein the pulse modulator includes:

M reset signal generators, each of which is configured to generate a reset signal defining an on-time of the switching transistor of a corresponding channel based on the error signal;

M set signal generators, each of which is configured to generate a set signal defining an off-time of the switching transistor of a corresponding channel; and

a logic circuit configured to generate the pulse modulated signals of the M channels based on the reset signals of the M channels and the set signals of the M channels.

13. The control circuit of claim 12, wherein the set signal generator of each of the M channels includes:

a zero-cross detection comparator configured to generate a zero-cross detection signal asserted when a current flowing in the inductor of a corresponding channel is zero; and

a delay circuit configured to delay the zero-cross detection signal to generate the set signal.

14. The control circuit of claim 13, wherein the zero-cross detection comparator of each of the M channels is further configured to generate the zero-cross detection signal based on a voltage at a node between the switching transistor and the inductor of the corresponding channel.

15. The control circuit of claim 13, wherein an amount of delay of the delay circuit is set based on an external circuit part.

16. A control method of a power factor correction circuit constituted by two channels, each of which includes a switching transistor, an inductor and a rectification element, the method comprising:

monitoring a total current of the two channels;

generating a mode control signal based on the total current;

amplifying an error of a feedback signal according to an output voltage of the power factor correction circuit and a target value of the feedback signal and generating an error signal;

generating a first pulse modulated signal and a second pulse modulated signal in a current critical mode in response to the error signal;

driving the switching transistor of a first channel based on the first pulse modulated signal; and

driving the switching transistor of a second channel based on the second pulse modulated signal,

wherein the act of generating a first pulse modulated signal and a second pulse modulated signal includes switching between a first mode in which a phase difference between the first pulse modulated signal and the second pulse modulated signal is 180° and

a second mode in which the phase difference between the first pulse modulated signal and the second pulse modulated signal is 360° and

the first channel and the second channel are exclusively and alternately used, in response to the mode control signal.

17. A control method of a power factor correction circuit constituted by M (M being an integer of two or more) channels, each of which includes a switching transistor, an inductor and a rectification element, the method comprising:

monitoring a total current of the two channels;

generating a mode control signal based on the total current;

amplifying an error of a feedback signal according to an output voltage of the power factor correction circuit and a target value of the feedback signal and generating an error signal;

generating pulse modulated signals of the M channels in a current critical mode in response to the error signal; and

driving the corresponding switching transistors of the M channels based on the corresponding pulse modulated signals, respectively,

wherein the act of generating pulse modulated signals of the M channels includes switching between a first mode in which the pulse modulated signals of the M channels sequentially transition to an on-level with a phase difference of 360°

/M and a second mode in which a plurality of consecutive switching periods are set as a period group, in response to the mode control signal, and, in each switching period included in the period group, a pulse modulated signal of one channel transitions to an on-level and then an off-level and pulse modulated signals of the remaining (M−

1) channels are kept at an off-level, and, during one period group, each pulse modulated signal transitions to the off-level at least once after transitioning to the on-level.