Driver circuit, display device including the driver circuit, and electronic appliance including the display device

• US 9,991,890 B2
• Filed: 07/28/2016
• Issued: 06/05/2018
• Est. Priority Date: 09/24/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Miyake, Hiroyuki
• Primary Examiner(s): O'Neill, Patrick
• Application Number:
  US15/221,845
• Publication Number:
  US 20170026039A1
• Time in Patent Office: 677 Days
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H03K 17/002 Switching arrangements with several input- or output terminals code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

An object of the present invention is to provide a driver circuit including a normally-on thin film transistor, which driver circuit ensures a small malfunction and highly reliable operation. The driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor. The first to third transistors each include a semiconductor layer of an oxide semiconductor and are depletion-mode transistors. An amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit.

Claims

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

an eighth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,

wherein the one of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the sixth transistor,

wherein a gate of the first transistor is electrically connected to a gate of the fourth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fifth transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the sixth transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the other of the source and the drain of the second transistor, and

wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the third transistor.

2. The semiconductor device according to claim 1,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the other of the source and the drain of the eighth transistor.

3. The semiconductor device according to claim 1, wherein a gate of the seventh transistor is electrically connected to a gate of the eighth transistor.

4. The semiconductor device according to claim 1, wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor has a lower UW ratio than each of the seventh transistor and the eighth transistor.

5. The semiconductor device according to claim 1, wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises an oxide semiconductor layer.

6. The semiconductor device according to claim 5, wherein the oxide semiconductor layer comprises indium and zinc.

7. A semiconductor device comprising a demultiplexer circuit connected to output terminals in each of pulse output circuits, the demultiplexer circuit comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor; and

a sixth transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor,

wherein the one of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the sixth transistor,

wherein a gate of the first transistor is electrically connected to a gate of the fourth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fifth transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the sixth transistor,

wherein the gate of the first transistor is electrically connected to at least one of the output terminals in each of pulse output circuits,

wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring, the first wiring being configured to supply a first signal,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a second wiring, the second wiring being configured to supply a second signal which is lower than the first signal,

wherein a gate of the second transistor is electrically connected to a third wiring, the third wiring being configured to supply a first control signal,

wherein a gate of the third transistor is electrically connected to a fourth wiring, the fourth wiring being configured to supply a second control signal,

wherein a gate of the fifth transistor is electrically connected to a fifth wiring, the fifth wiring being configured to supply an inversion signal of the first control signal,

wherein a gate of the sixth transistor is electrically connected to a sixth wiring, the sixth wiring being configured to supply an inversion signal of the second control signal,

wherein the other of the source and the drain of the second transistor is electrically connected to a first output terminal, and

wherein the other of the source and the drain of the third transistor is electrically connected to a second output terminal.

8. The semiconductor device according to claim 7, further comprising a seventh transistor and an eighth transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to the other of the source and the drain of the second transistor,

wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the third transistor, and

wherein the other of the source and the drain of the seventh transistor is electrically connected to the other of the source and the drain of the eighth transistor.

9. The semiconductor device according to claim 8, wherein a gate of the seventh transistor is electrically connected to a gate of the eighth transistor.

10. The semiconductor device according to claim 8, wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor has a lower L/W ratio than each of the seventh transistor and the eighth transistor.

11. The semiconductor device according to claim 7, wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises an oxide semiconductor layer.

12. The semiconductor device according to claim 11, wherein the oxide semiconductor layer comprises indium and zinc.

13. A demultiplexer circuit comprising a first transistor and a second transistor each comprising an oxide semiconductor layer,

wherein the second transistor has lower L/W ratio than the first transistor.

14. The demultiplexer circuit according to claim 13,

wherein the oxide semiconductor layer comprises indium and zinc.

15. A driver circuit comprising:

a static shift register; and

a demultiplexer circuit connected to an output terminal of the static shift register,

wherein the demultiplexer circuit comprises a first transistor and a second transistor each comprising an oxide semiconductor layer, and

wherein the second transistor has lower L/W ratio than the first transistor.

16. The driver circuit according to claim 15,

wherein the oxide semiconductor layer comprises indium and zinc.