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Multidirectional semiconductor arrangement testing

  • US 9,995,770 B2
  • Filed: 03/21/2014
  • Issued: 06/12/2018
  • Est. Priority Date: 03/21/2014
  • Status: Active Grant
First Claim
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1. A semiconductor testing arrangement, comprising:

  • a probe card comprising;

    a first pin arrangement comprising a first set of linearly arranged pins aligned in a first direction; and

    a second pin arrangement comprising a second set of linearly arranged pins aligned in a second direction; and

    a semiconductor wafer comprising;

    a first set of pads for mating with the first set of linearly arranged pins and aligned in the first direction, wherein the first set of pads is disposed between a first integrated circuit and a second integrated circuit that is immediately adjacent the first integrated circuit;

    a second set of pads for mating with the first set of linearly arranged pins and aligned in the first direction, wherein;

    the second set of pads is disposed between the first integrated circuit and the second integrated circuit,the first set of pads is offset from the second set of pads in the second direction perpendicular to the first direction, andthe first set of pads is offset in the first direction from the second set of pads;

    a third set of pads for mating with the second set of linearly arranged pins and aligned in the second direction, wherein the third set of pads is disposed between the first integrated circuit and a third integrated circuit that is immediately adjacent the first integrated circuit; and

    a fourth set of pads for mating with the second set of linearly arranged pins and aligned in the second direction, wherein;

    the fourth set of pads is disposed between the first integrated circuit and the third integrated circuit,the third set of pads is offset in the first direction from the fourth set of pads, andthe third set of pads is offset in the second direction from the fourth set of pads.

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