Multidirectional semiconductor arrangement testing

• US 9,995,770 B2
• Filed: 03/21/2014
• Issued: 06/12/2018
• Est. Priority Date: 03/21/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lo, Tseng-Chin, Tseng, Huan Chi, Chang, Kuo-Chuan, Chang, Yuan-Yao, Lee, Chien-Chang
• Primary Examiner(s): Nguyen, Tung X
• Assistant Examiner(s): Rodak, Lee
• Application Number:
  US14/221,543
• Publication Number:
  US 20150268271A1
• Time in Patent Office: 1,544 Days
• Field of Search: 32475401-7542, 32475501-75511, 32475601-75607, 32476205, 32476206
• CPC Class Codes: G01R 1/0491 for testing integrated circuits on wafers, e.g. wafer-level test cartridge
• CPC Class Codes: G01R 1/07364 with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence

Abstract

One or more probe cards, wafer testers, and techniques for testing a semiconductor arrangement are provided. Testline arrangements are formed within scribe lines of a semiconductor wafer, in multiple directions, such as an x-direction and a y-direction. A wafer tester is configured to concurrently test the semiconductor arrangement in multiple directions using a multidirectional probe arrangement of a probe card. In some embodiments, a first pin arrangement of the multidirectional probe arrangement is mated with a first testline arrangement in a first direction, and a second pin arrangement of the multidirectional probe arrangement is mated with a second testline arrangement in a second direction. The wafer tester concurrently tests the semiconductor arrangement in multiple directions, such as in the first direction and the second direction, through the pin arrangements mated with the testline arrangements.

Claims

1. A semiconductor testing arrangement, comprising:

a probe card comprising;

a first pin arrangement comprising a first set of linearly arranged pins aligned in a first direction; and

a second pin arrangement comprising a second set of linearly arranged pins aligned in a second direction; and

a semiconductor wafer comprising;

a first set of pads for mating with the first set of linearly arranged pins and aligned in the first direction, wherein the first set of pads is disposed between a first integrated circuit and a second integrated circuit that is immediately adjacent the first integrated circuit;

a second set of pads for mating with the first set of linearly arranged pins and aligned in the first direction, wherein;

the second set of pads is disposed between the first integrated circuit and the second integrated circuit,

the first set of pads is offset from the second set of pads in the second direction perpendicular to the first direction, and

the first set of pads is offset in the first direction from the second set of pads;

a third set of pads for mating with the second set of linearly arranged pins and aligned in the second direction, wherein the third set of pads is disposed between the first integrated circuit and a third integrated circuit that is immediately adjacent the first integrated circuit; and

a fourth set of pads for mating with the second set of linearly arranged pins and aligned in the second direction, wherein;

the fourth set of pads is disposed between the first integrated circuit and the third integrated circuit,

the third set of pads is offset in the first direction from the fourth set of pads, and

the third set of pads is offset in the second direction from the fourth set of pads.

2. The semiconductor testing arrangement of claim 1, wherein the first set of pads is formed along a first scribe line of the semiconductor wafer.

3. The semiconductor testing arrangement of claim 1, wherein the first pin arrangement is configured to perform a first test using the first set of pads and the second pin arrangement configured to perform a second test using the third set of pads concurrently with the first test.

4. The semiconductor testing arrangement of claim 1, wherein:

the first pin arrangement is configured to perform a first test using the first set of pads and the second pin arrangement is configured to perform a second test using the third set of pads concurrently with the first test; and

the first pin arrangement is configured to perform a third test using the second set of pads and the second pin arrangement is configured to perform a fourth test using the fourth set of pads concurrently with the third test.

5. The semiconductor testing arrangement of claim 1, wherein:

the probe card comprises a third pin arrangement comprising a third set of linearly arranged pins aligned in the first direction,

the semiconductor wafer comprises;

a fifth set of pads for mating with the third set of linearly arranged pins and aligned in the first direction; and

a sixth set of pads for mating with the third set of linearly arranged pins and aligned in the first direction,

the fifth set of pads is disposed between the third integrated circuit and a fourth integrated circuit that is immediately adjacent the third integrated circuit,

the sixth set of pads is disposed between the third integrated circuit and the fourth integrated circuit,

a first region devoid of pads extends between a first pad of the first set of pads and a second pad of the fifth set of pads that is nearest the first pad in the first direction,

a second region devoid of pads extends between a third pad of the second set of pads and a fourth pad of the sixth set of pads that is nearest the third pad in the first direction, and

a width of the first region, measured from the first pad to the second pad, is equal to a width of the second region, measured from the third pad to the fourth pad.

6. A method for testing a semiconductor arrangement, comprising:

utilizing a multidirectional probe arrangement to concurrently test a first testline arrangement and a second testline arrangement, comprising;

mating a first set of linearly arranged pins of the multidirectional probe arrangement aligned in a first direction with a first set of pads of the first testline arrangement aligned in the first direction and disposed between a first integrated circuit and a second integrated circuit that is immediately adjacent the first integrated circuit; and

mating a second set of linearly arranged pins of the multidirectional probe arrangement aligned in a second direction, different than the first direction, with a second set of pads of the second testline arrangement aligned in the second direction and disposed between the first integrated circuit and a third integrated circuit that is immediately adjacent the first integrated circuit; and

utilizing the multidirectional probe arrangement to concurrently test a third testline arrangement and a fourth testline arrangement, comprising;

mating the first set of linearly arranged pins with a third set of pads aligned in the first direction and offset in the first direction from the first set of pads while the first set of linearly arranged pins is not mated with the first set of pads,

wherein the third set of pads is disposed between the first integrated circuit and the second integrated circuit; and

mating the second set of linearly arranged pins with a fourth set of pads aligned in the second direction and offset in the second direction from the second set of pads while the second set of linearly arranged pins is unmated from the first set of pads, wherein the fourth set of pads is disposed between the first integrated circuit and the third integrated circuit.

7. The method of claim 6, wherein the utilizing a multidirectional probe arrangement to concurrently test a first testline arrangement and a second testline arrangement comprises:

utilizing the multidirectional probe arrangement to test a fifth testline arrangement concurrently with the first testline arrangement and the second testline arrangement.

8. The method of claim 7, wherein the utilizing a multidirectional probe arrangement to test a fifth testline arrangement comprises:

mating a third set of linearly arranged pins of the multidirectional probe arrangement aligned in the first direction with a fifth set of pads of the fifth testline arrangement aligned in the first direction and disposed between the third integrated circuit and a fourth integrated circuit.

9. The method of claim 6, wherein the second set of linearly arranged pins is perpendicular to the first set of linearly arranged pins.

10. A semiconductor testing arrangement, comprising:

a semiconductor wafer comprising;

a first set of pads aligned in a first direction for mating with a first set of linearly arranged pins of a probe card, wherein the first set of pads is disposed between a first integrated circuit and a second integrated circuit that is immediately adjacent the first integrated circuit;

a second set of pads aligned in the first direction for mating with the first set of linearly arranged pins, wherein;

the second set of pads is disposed between the first integrated circuit and the second integrated circuit,

the first set of pads is offset from the second set of pads in a second direction different than the first direction, and

the first set of pads is offset in the first direction from the second set of pads;

a third set of pads aligned in the second direction for mating with a second set of linearly arranged pins of the probe card, wherein the third set of pads is disposed between the first integrated circuit and a third integrated circuit that is immediately adjacent the first integrated circuit; and

a fourth set of pads aligned in the second direction for mating with the second set of linearly arranged pins, wherein;

the fourth set of pads is disposed between the first integrated circuit and the third integrated circuit, and

the third set of pads is offset in the second direction from the fourth set of pads.

11. The semiconductor testing arrangement of claim 10, wherein the second direction is perpendicular to the first direction.

12. The semiconductor testing arrangement of claim 10, wherein:

the semiconductor wafer comprises a fifth set of pads aligned in the first direction for mating with a third set of linearly arranged pins of the probe card, and

the fifth set of pads is disposed between the third integrated circuit and a fourth integrated circuit.

13. The semiconductor testing arrangement of claim 12, wherein the fifth set of pads is aligned for mating with the third set of linearly arranged pins concurrently with the first set of pads mating with the first set of linearly arranged pins.

14. The semiconductor testing arrangement of claim 10, wherein:

the third set of pads is aligned for mating with the second set of linearly arranged pins concurrently with the first set of pads mating with the first set of linearly arranged pins; and

the fourth set of pads is aligned for mating with the second set of linearly arranged pins concurrently with the second set of pads mating with the first set of linearly arranged pins.

15. The semiconductor testing arrangement of claim 10, wherein:

the semiconductor wafer comprises;

a fifth set of pads for mating with a third set of linearly arranged pins and aligned in the first direction; and

a sixth set of pads for mating with the third set of linearly arranged pins and aligned in the first direction.

16. The semiconductor testing arrangement of claim 15, wherein the fifth set of pads is disposed between the third integrated circuit and a fourth integrated circuit that is immediately adjacent the second integrated circuit and the third integrated circuit.

17. The semiconductor testing arrangement of claim 16, wherein the sixth set of pads is disposed between the third integrated circuit and the fourth integrated circuit.

18. The semiconductor testing arrangement of claim 15, wherein:

a first region devoid of pads extends between a first pad of the first set of pads and a second pad of the fifth set of pads that is nearest the first pad in the first direction,

a second region devoid of pads extends between a third pad of the second set of pads and a fourth pad of the sixth set of pads that is nearest the third pad in the first direction, and

a width of the first region, measured from the first pad to the second pad, is equal to a width of the second region, measured from the third pad to the fourth pad.

19. The semiconductor testing arrangement of claim 10, wherein the first set of pads is formed along a first scribe line of the semiconductor wafer.

20. The semiconductor testing arrangement of claim 19, wherein the second set of pads is formed along a second scribe line of the semiconductor wafer.