Storage system with distributed ECC capability

• US 9,996,419 B1
• Filed: 05/09/2015
• Issued: 06/12/2018
• Est. Priority Date: 05/18/2012
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Inventors: Bruce, Rey H., Climaco, Joey B., Mateo, Noeme P.
• Primary Examiner(s): Tu, Christine T.
• Application Number:
  US14/708,246
• Time in Patent Office: 1,130 Days
• Field of Search: 714767, 714769, 714770, 714772, 714773, 714757, 714747, 714751, 714763, 714764, 714766, 714799, 714800, 714801, 714820, 714701, 714 62, 714 621, 714 6, 714 23, 714 624, 714 54, 714 52, 714 42, 365200, 365201, 711111, 711112
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: H03M 13/27 using interleaving techniques

Abstract

Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an apparatus for handling distributed error correction code (ECC) operations, includes: a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts; the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices; and the plurality of ECC engines configured to use respective ECC bytes corresponding to respective ones of the multiple data parts.

Claims

1. An apparatus for handling distributed error correction code (ECC) operations, the apparatus comprising:

a storage system configured to partition a contiguous data into multiple data parts including a first data part and a second data part;

the storage system comprising;

a plurality of ECC engines configured to perform ECC operations in parallel on the multiple data parts, wherein the plurality of ECC engines comprises a first ECC engine and a second ECC engine;

wherein the first ECC engine is configured to compute a first computed ECC part for the first data part and the second ECC engine is configured to compute a second computed ECC part for the second data part;

wherein the plurality of ECC engines is distributed in parallel; and

a plurality of storage interface controllers comprising a first storage interface controller and a second storage interface controller;

wherein the first storage interface controller is configured to write or read the first data part and the first computed ECC part in a first storage media device in a first group of storage media devices comprising a first plurality of storage media devices;

wherein the second storage interface controller is configured to write or read the second data part and the second computed ECC part in a second storage media device in a second group of storage media devices comprising a second plurality of storage media devices;

wherein the storage media devices are coupled to the plurality of storage interface controllers and the plurality of storage interface controllers are coupled to the plurality of ECC engines;

wherein the first storage interface controller comprises a first logic to provide a first path between the first storage media device and the first ECC engine for the first data part and first computed ECC part;

wherein the second storage interface controller comprises a second logic to provide a second path between the second storage media device and the second ECC engine for the second data part and second computed ECC part.

2. The apparatus of claim 1, wherein the ECC engines are included in a storage DMA (direct memory access) controller.

3. The apparatus of claim 2, wherein the storage DMA controller includes a DMA &

ECC instruction buffer configured to store DMA instructions for use in DMA operations and ECC configurations for use in ECC operations.

4. The apparatus of claim 2, wherein the storage DMA controller includes a data path &

ECC configuration control block configured to permit DMA operations with distributed ECC.

5. The apparatus of claim 1, wherein the apparatus further comprises a local memory system configured to store the multiple data parts that are to be written to the storage media devices.

6. The apparatus of claim 1, wherein the multiple data parts are written to different locations in the storage media devices.

7. The apparatus of claim 6, wherein the different locations comprises different groups in the storage media devices.

8. The apparatus of claim 1, wherein the multiple data parts are read from different locations in the storage media devices.

9. The apparatus of claim 8, wherein the different locations comprises different groups in the storage media devices.

10. The apparatus of claim 1, wherein the multiple data parts comprises partitions in a data block.

11. The apparatus of claim 1, wherein the plurality of ECC engines has a respective ECC engine that performs an ECC operation on a respective data part in the multiple data parts.

12. The apparatus of claim 1, wherein an ECC operation comprises an ECC encode operation.

13. The apparatus of claim 1, wherein an ECC operation comprises an ECC detect operation.

14. The apparatus of claim 1, wherein an ECC operation comprises an ECC correct operation.

15. The apparatus of claim 1, wherein the ECC engines comprise a plurality of ECC encode and detect modules and a plurality of ECC correct modules, wherein a given subset of the plurality of ECC encode and detect modules is coupled to and is sharing a given ECC correct module of the plurality of ECC correct modules.

16. The apparatus of claim 15, wherein the ECC engines are included in a storage DMA controller.

17. The apparatus of claim 1, wherein an ECC engine will compute a respective ECC byte for a respective data part.

18. The apparatus of claim 1, wherein the storage media devices comprise non-volatile memory devices.

19. A method for handling distributed error correction code (ECC) operations, the method comprising:

partitioning a contiguous data into multiple data parts including a first data part and a second data part;

performing ECC operations in parallel on multiple data parts comprising computing, by a first ECC engine a first computed ECC part for the first data part and computing, by a second ECC engine, a second computed ECC part for the second data part, wherein a plurality of ECC engines comprises the first ECC engine and the second ECC engine; and

wherein a plurality of storage interface controllers comprises a first storage interface controller and a second storage interface controller;

wherein the first storage interface controller is configured to write or read the first data part and the first computed ECC part in a first storage media device in a first group of storage media devices comprising a first plurality of storage media devices;

wherein the second storage interface controller is configured to write or read the second data part and the second computed ECC part in a second storage media device in a second group of storage media devices comprising a second plurality of storage media devices;

wherein the storage media devices are coupled to the plurality of storage interface controllers and the plurality of storage interface controllers are coupled to the plurality of ECC engines for performing the ECC operations;

wherein the first storage interface controller comprises a first logic to provide a first path between the first storage media device and the first ECC engine for the first data part and first computed ECC part;

wherein the second storage interface controller comprises a second logic to provide a second path between the second storage media device and the second ECC engine for the second data part and second computed ECC part.

20. An article of manufacture, comprising:

a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising;

partitioning a contiguous data into multiple data parts including a first data part and a second data part;

performing ECC operations in parallel on multiple data parts comprising computing, by a first ECC engine, a first computed ECC part for the first data part and computing, by a second ECC engine, a second computed ECC part for the second data part, wherein a plurality of ECC engines comprises the first ECC engine and the second ECC engine; and

wherein a plurality of storage interface controllers comprises a first storage interface controller and a second storage interface controller;

wherein the first storage interface controller is configured to write or read the first data part and the first computed ECC part in a first storage media device in a first group of storage media devices comprising a first plurality of storage media devices;

wherein the second storage interface controller is configured to write or read the second data part and the second computed ECC part in a second storage media device in a second group of storage media devices comprising a second plurality of storage media devices;

wherein the storage media devices are coupled to the plurality of storage interface controllers and the plurality of storage interface controllers are coupled to the plurality of ECC engines for performing the ECC operations;

wherein the first storage interface controller comprises a first logic to provide a first path between the first storage media device and the first ECC engine for the first data part and first computed ECC part;

wherein the second storage interface controller comprises a second logic to provide a second path between the second storage media device and the second ECC engine for the second data part and second computed ECC part.

21. A method for handling distributed error correction code (ECC) operations, the method comprising:

partitioning a contiguous data into multiple data parts;

wherein the multiple data parts comprises a first data part and a second data part;

performing ECC operations in parallel on the multiple data parts, comprising;

in parallel, performing an ECC operation on the first data part including computing a first computed ECC part and performing another ECC operation on the second data part including computing a second computed ECC part; and

writing or reading the first data part and the first computed ECC part in a first storage media device in a first group of storage media devices comprising a first plurality of storage media devices;

writing or reading the second data part and the second computed ECC part in a second storage media device in a second group of storage media devices comprising a second plurality of storage media devices;

wherein a first storage interface controller comprises a first logic to provide a first path between the first storage media device and a first ECC engine for the first data part and first computed ECC part;

wherein a second storage interface controller comprises a second logic to provide a second path between the second storage media device and a second ECC engine for the second data part and second computed ECC part.

22. An article of manufacture, comprising:

a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising;

partitioning a contiguous data into multiple data parts;

wherein the multiple data parts comprises a first data part and a second data part;

performing ECC (error correction code) operations in parallel on the multiple data parts, comprising;

in parallel, performing an ECC operation on the first data part including computing a first computed ECC part and performing another ECC operation on the second data part including computing a second computed ECC part; and

writing or reading the first data part and the first computed ECC part in a first storage media device in a first group of storage media devices comprising a first plurality of storage media devices;

writing or reading the second data part and the second computed ECC part in a second storage media device in a second group of storage media devices comprising a second plurality of storage media devices;

wherein a first storage interface controller comprises a first logic to provide a first path between the first storage media device and a first ECC engine for the first data part and first computed ECC part;

wherein a second storage interface controller comprises a second logic to provide a second path between the second storage media device and a second ECC engine for the second data part and second computed ECC part.

23. An apparatus, comprising:

a storage system configured to partition a contiguous data into multiple data parts;

wherein the multiple data parts comprises a first data part and a second data part;

a plurality of ECC (error correction code) engines configured to perform ECC operations in parallel on the multiple data parts, wherein the plurality of ECC engines comprises a first ECC engine and a second ECC engine;

wherein, in parallel, the first ECC engine is configured to perform an ECC operation on the first data part including computing a first computed ECC part and the second ECC engine is configured to perform another ECC operation on the second data part including computing a second computed ECC part; and

a first storage interface controller configured to write or read the first data part and the first computed ECC part in a first storage media device in a first group of storage media devices comprising a first plurality of storage media devices;

a second storage interface controller configured to write or read the second data part and the second computed ECC part in a second storage media device in a second group of storage media devices comprising a second plurality of storage media devices;

wherein the first storage interface controller comprises a first logic to provide a first path between the first storage media device and the first ECC engine for the first data part and first computed ECC part;

wherein the second storage interface controller comprises a second logic to provide a second path between the second storage media device and the second ECC engine for the second data part and second computed ECC part.