EL display apparatus

• US 9,997,108 B1
• Filed: 01/25/2018
• Issued: 06/12/2018
• Est. Priority Date: 09/07/2001
• Status: Expired due to Term

• Current Assignee: JOLED Inc.
• Original Assignee: JOLED Inc.
• Inventors: Takahara, Hiroshi, Tsuge, Hitoshi
• Primary Examiner(s): Sitta, Grant
• Assistant Examiner(s): Bogale, Amen
• Application Number:
  US15/879,899
• Publication Number:
  US 20180166014A1
• Time in Patent Office: 138 Days
• CPC Class Codes: G09G 2300/0404 Matrix technologies
• CPC Class Codes: G09G 2300/0413 Details of dummy pixels or dummy lines in flat panels
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/0218 with collection of electrodes in groups for n-dimensional addressing
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0256 with the purpose of reversing the voltage across a light emitting or modulating element within a pixel
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2320/0257 Reduction of after-image effects
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2320/06 : Adjustment of display parameters
• CPC Class Codes: G09G 2320/0606 : Manual adjustment
• CPC Class Codes: G09G 2320/0626 : for control of overall brightness
• CPC Class Codes: G09G 2320/0646 : Modulation of illumination source brightness and image signal correlated to each other
• CPC Class Codes: G09G 2320/0653 : Controlling or limiting the speed of brightness adjustment of the illumination source
• CPC Class Codes: G09G 3/2003 : Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/2007 : Display of intermediate tones
• CPC Class Codes: G09G 3/32 : semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/3233 : with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3241 : the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
• CPC Class Codes: G09G 3/325 : the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
• CPC Class Codes: G09G 3/3258 : with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3266 : Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3275 : Details of drivers for data electrodes
• CPC Class Codes: G09G 5/02 : characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: H01L 27/124 : with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 : comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 : integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/127 : with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/156 : two-dimensional arrays
• CPC Class Codes: H01L 29/78645 : with multiple gate
• CPC Class Codes: H01L 29/78672 : Polycrystalline or microcrystalline silicon transistor
• CPC Class Codes: H01L 33/56 : Materials, e.g. epoxy or silicone resin
• CPC Class Codes: H01L 33/58 : Optical field-shaping elements
• CPC Class Codes: H10K 50/8428 : Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
• CPC Class Codes: H10K 50/844 : Encapsulations
• CPC Class Codes: H10K 50/846 : comprising getter material or desiccants
• CPC Class Codes: H10K 50/86 : Arrangements for improving contrast, e.g. preventing reflection of ambient light
• CPC Class Codes: H10K 59/12 : Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 : the pixel elements being capacitors
• CPC Class Codes: H10K 59/126 : Shielding, e.g. light-blocking means over the TFTs
• CPC Class Codes: H10K 59/35 : comprising red-green-blue [RGB] subpixels
• CPC Class Codes: H10K 59/352 : the areas of the RGB subpixels being different

Abstract

An electroluminescent (EL) display apparatus and method are provided. A display screen includes pixels. A pixel circuit of each of pixel includes, in part: a first switch transistor on a path through which current flows from a power line through a driving transistor to an EL device; a second switch transistor to supply an image signal to the driving transistor; and a third switch transistor for initially resetting the pixel circuit before the second switch transistor supplies the image signal. A gate terminal of the first switch transistor is connected to a first gate driver circuit. Gate terminals of the second and third switch transistors are connected to a second gate driver circuit, which includes a second gate signal line connected to both the gate terminal of the second switch transistor of a Nth row and the gate terminal of the third switch transistor of a (N+1)th row.

Claims

1. An electroluminescent (EL) display apparatus, comprising:

a display screen including pixels arranged in a matrix, each of the pixels including an EL device and a pixel circuit;

a source signal line through which an analog image signal output from a source driver circuit is transmitted; and

a gate driver circuit which includes a first gate driver circuit and a second gate driver circuit, first gate signal lines through which selection voltages and non-selection voltages output from the first gate driver circuit are transmitted, and second gate signal lines through which selection voltages and non-selection voltages output from the second gate driver circuit are transmitted;

wherein the pixel circuit of each of the pixels includes;

a driving transistor to supply a current to the EL device;

a first switch transistor provided on a current path through which the current flows from a power line through the driving transistor to the EL device;

a second switch transistor to supply, to the driving transistor, the analog image signal supplied from the source signal line; and

a third switch transistor for initially resetting the pixel circuit before the second switch transistor supplies, to the driving transistor, the analog image signal supplied from the source signal line,

a gate terminal of the first switch transistor is connected to the first gate driver circuit,

a gate terminal of the second switch transistor and a gate terminal of the third switch transistor are connected to the second gate driver circuit,

the second gate driver circuit includes a second gate signal line connected to both the gate terminal of the second switch transistor of a Nth pixel row and the gate terminal of the third switch transistor of a (N+1)th pixel row for simultaneously connecting the gate terminal of the second switch transistor of the Nth pixel row and the gate terminal of the third switch transistor of the (N+1)th pixel row, and

the first switch transistor of the (N+1)th pixel row is controlled in an OFF state by the first gate driver circuit when the third switch transistor initially resets the pixel circuit.

2. The EL display apparatus according to claim 1, further comprising:

the source driver circuit connected to the source signal line,

wherein the source driver circuit is configured to supply a signal voltage to a gate of the driving transistor to flow a current which is N times as large as a predetermined value to the EL device to achieve a gray scale display indicated by the analog image signal, and

N is greater than one.

3. The EL display apparatus according to claim 1, further comprising:

a precharge circuit or a discharge circuit which forcibly charges or discharges the source signal line.

4. The EL display apparatus according to claim 1,

wherein, by the first gate driver circuit and the second gate driver circuit, the first switch transistor is independently on/off controlled from the second switch transistor and the third switch transistor.

5. The EL display apparatus according to claim 1,

wherein the first gate driver circuit is configured to select a plurality of the first gate signal lines simultaneously.

6. The EL display apparatus according to claim 1,

wherein the first gate signal lines are divided into a plurality of blocks,

a plurality of first gate signal lines in one block is connected as one control line, and

the first gate driver circuit is configured to select the plurality of first gate signal lines as a block simultaneously.

7. The EL display apparatus according to claim 1,

wherein the third switch transistor initially resets a gate terminal of the driving transistor before the second switch transistor supplies, to the driving transistor, the analog image signal supplied from the source signal line.

8. The EL display apparatus according to claim 7,

wherein the third switch transistor initially resets the gate terminal of the driving transistor by shorting the gate terminal of the driving transistor and a drain terminal of the driving transistor.

9. The EL display apparatus according to claim 7,

wherein the third switch transistor initially resets the gate terminal of the driving transistor by shorting the gate terminal of the driving transistor and an initial reset voltage line.

10. The EL display apparatus according to claim 9,

a voltage of the initial reset voltage line is a predetermined constant voltage.

11. The EL display apparatus according to claim 1,

the first switch transistor of the Nth pixel row is controlled in an OFF state by the first gate driver circuit.

12. The EL display apparatus according to claim 1,

the first switch transistor, the second switch transistor, and third switch transistor are P channel transistors.

13. The EL display apparatus according to claim 1,

the second gate driver circuit connecting the gate terminal of the third switch transistor of the Nth pixel row, and sequentially connecting the gate terminal of the second switch transistor of the Nth pixel row, are synchronized with a 1H synchronization signal.

14. The EL display apparatus according to claim 1,

the second gate driver circuit connecting the gate terminal of the third switch transistor of the (N+1)th pixel row, and sequentially connecting the gate terminal of the second switch transistor of the (N+1)th pixel row, are synchronized with a 1H synchronization signal.

15. An electronic device, comprising:

the EL display apparatus according to claim 1.

16. A method of controlling an electroluminescent (EL) display apparatus,

the EL display apparatus comprising:

a display screen including pixels arranged in a matrix, each of the pixels including an EL device and a pixel circuit;

a source signal line through which an analog image signal output from a source driver circuit is transmitted; and

a gate driver circuit which includes a first gate driver circuit and a second gate driver circuit, first gate signal lines through which selection voltages and non-selection voltages output from the first gate driver circuit are transmitted, and second gate signal lines through which selection voltages and non-selection voltages output from the second gate driver circuit are transmitted,

the pixel circuit of each of the pixels including;

a driving transistor to supply a current to the EL device;

a first switch transistor provided on a current path through which the current flows from a power line through the driving transistor to the EL device;

a second switch transistor to supply, to the driving transistor, the analog image signal supplied from the source signal line; and

a third switch transistor for initially resetting the pixel circuit before the second switch transistor supplies, to the driving transistor, the analog image signal supplied from the source signal line,

a gate terminal of the first switch transistor is connected to the first gate driver circuit,

a gate terminal of the second switch transistor and a gate terminal of the third switch transistor are connected to the second gate driver circuit,

the second gate driver circuit includes a second gate signal line connected to both the gate terminal of the second switch transistor of a Nth pixel row and the gate terminal of the third switch transistor of a (N+1)th pixel row for simultaneously connecting the gate terminal of the second switch transistor of the Nth pixel row and the gate terminal of the third switch transistor of the (N+1)th pixel row,

the method comprising;

programming, by the second gate driver circuit and during a period, a first pixel of the Nth pixel row with a voltage by applying an on-voltage to the second gate signal line to turn on the second switch transistor of the first pixel;

resetting, by the second gate driver circuit and during the period, a second pixel of the (N+1)th pixel row by applying the on-voltage to the second gate signal line to simultaneously turn on the third switch transistor of the second pixel; and

controlling the first switch transistor of the (N+1)th pixel row in an OFF state by the first gate driver circuit when the third switch transistor initially resets the pixel circuit.

17. The method according to claim 16,

wherein a gate terminal of the driving transistor is reset by the resetting of the second pixel.

18. The method according to claim 16,

wherein the third switch transistor initially resets a gate terminal of the driving transistor before the second switch transistor supplies, to the driving transistor, the analog image signal supplied from the source signal line.

19. The method according to claim 18,

wherein the gate terminal of the driving transistor is reset by shorting the gate terminal of the driving transistor and an initial reset voltage line.

20. The method according to claim 16,

wherein the first gate signal lines are divided in a plurality of blocks,

a plurality of first gate signal lines in one block is connected as one control line, and

the method comprises:

selecting, by the first gate driver circuit, the plurality of first gate signal lines as a block simultaneously.