Accessing data in memory

• US 9,997,212 B1
• Filed: 04/24/2017
• Issued: 06/12/2018
• Est. Priority Date: 04/24/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Finkbeiner, Timothy P., Hush, Glen E., Pinney, David L.
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/494,879
• Time in Patent Office: 414 Days
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/229 Timing of a write operation
• CPC Class Codes: G11C 2211/4013 Memory devices with multiple cells per bit, e.g. twin-cells
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

The present disclosure includes apparatuses and methods related to accessing data in memory. One example method comprises storing data associated with a first operation in a first sense amplifier responsive to receiving a request to perform a second operation, and performing the second operation associated with a row of memory cells while the data associated with the first operation is being stored in the first sense amplifier.

Claims

1. A method, comprising:

storing data associated with a first operation in a first sense amplifier responsive to receiving a request to perform a second operation; and

performing the second operation associated with a row of memory cells while the data associated with the first operation is stored in the first sense amplifier.

2. The method of claim 1, wherein the method includes performing the second operation associated with the row of memory cells without storing the data associated with the first operation in the row of memory cells.

3. The method of claim 1, wherein performing the second operation associated with the row includes accessing the row by a second sense amplifier.

4. The method of claim 3, wherein the method includes equilibrating columns coupled to the row prior to accessing the row by the second sense amplifier.

5. The method of claim 1, wherein the first operation is a compute operation.

6. The method of claim 1, wherein the second operation is a memory operation.

7. An apparatus, comprising:

a controller; and

sensing circuitry of an array of memory cells and controlled by the controller to;

store data associated with a first operation in the sensing circuitry responsive to receiving a request to perform a second operation associated with a row of the array; and

perform the second operation associated with the row of the array while the data associated with the first operation is being stored in the sensing circuitry.

8. The apparatus of claim 7, wherein the sensing circuitry of the array of memory cells comprises a first sense amplifier and a second sense amplifier.

9. The apparatus of claim 8, wherein the controller is configured to control the sensing circuitry to store the data associated with the first operation in the first sense amplifier until a completion of the second operation.

10. The apparatus of claim 8, wherein the controller is configured to control the sensing circuitry to continue performing the first operation by the first sense amplifier while performing the second operation by the second amplifier.

11. The apparatus of claim 7, wherein the controller is configured to control the sensing circuitry to perform the second operation associated with the row of the array without storing the data associated with the first operation in the array of memory cells.

12. The apparatus of claim 7, wherein the controller is configured to control the sensing circuitry to equilibrate columns coupled to the row responsive to receiving the request to perform the second operation on the memory cell of the array.

13. A method, comprising:

performing a first operation responsive to receiving a request to perform a second operation associated with a row of memory cells; and

enabling a first sense amplifier without storing data associated with the first operation in the row of memory cells.

14. The method of claim 13, wherein the enabling the first sense amplifier without storing the data associated with the first operation in the row of memory cells includes storing the data associated with the first operation in the first sense amplifier upon enabling the first sense amplifier.

15. The method of claim 14, wherein the method includes performing the second operation associated with the row by a second sense amplifier while the data associated with first operation is being stored in the first sense amplifier.

16. The method of claim 13, wherein the method includes equilibrating columns coupled to the row upon enabling the first sense amplifier.

17. The method of claim 16, wherein the method includes initiating the second operation responsive to the corresponding columns being equilibrated.

18. The method of claim 13, wherein the method includes accessing the row of memory cells upon a completion of the second operation to continue performing the first operation.

19. An apparatus, comprising:

a controller; and

sensing circuitry including a first sense amplifier and a second sense amplifier, and wherein the controller is configured to control the sensing circuitry to;

enable the first sense amplifier without storing data associated with a first operation in a row of memory cells responsive to, while performing the first operation, receiving a request to perform a second operation; and

equilibrate the columns coupled to the row of memory cells.

20. The apparatus of claim 19, wherein the request to perform the second operation is received from a host.

21. The apparatus of claim 19, wherein the controller is configured to control the sensing circuitry to perform the second operation by the second sense amplifier.

22. The apparatus of claim 19, wherein the sensing circuitry includes a compute component, and wherein the controller is configured to control the sensing circuitry to perform the second operation without using the compute component.

23. The apparatus of claim 19, wherein the controller is configured to control the sensing circuitry to perform memory operations and compute operations.

24. The apparatus of claim 19, wherein the first operation is a compute operation.

25. The apparatus of claim 19, wherein the second operation is a memory operation.

26. The apparatus of claim 19, wherein the apparatus is a processing in memory (PIM) device.