10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of operation thereof

• US 9,997,237 B2
• Filed: 04/13/2017
• Issued: 06/12/2018
• Est. Priority Date: 10/21/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Tandingan, Joseph S, Still, David W., Siman, Jesse J, Ashokkumar, Jayant
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Leboeuf, Jerome
• Application Number:
  US15/487,071
• Publication Number:
  US 20170263309A1
• Time in Patent Office: 425 Days
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence

Abstract

A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

Claims

1. A memory comprising:

an array of non-volatile Static Random Access Memory (nvSRAM) cells, each nvSRAM cell comprising;

a volatile charge storage circuit; and

a non-volatile charge storage circuit comprising a non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a first positive voltage supply line (VCCT);

a fourth transistor coupled between a negative voltage supply line (VSSI) in the volatile charge storage circuit and a negative voltage supply (VSS); and

a processing element configured to issue control signals to each of the nvSRAM cells to execute a STORE operation and a RECALL operation, the control signals including a signal to the fourth transistor to electrically disconnect the VSSI from the VSS during the RECALL operation.

2. The memory of claim 1, wherein the non-volatile charge storage circuit in each nvSRAM comprises exactly one NVM element.

3. The memory of claim 2, wherein the control signals comprise signals for normal programming in which the first transistor is ON and the second and third transistors are OFF, and a plurality of pulses are applied to a gate node of the NVM element.

4. The memory of claim 3, wherein the processing element is further configured to issue control signals for the STORE operation comprising signals for bulk programming to set the NVM element to a programmed state, and signals for bulk erasing to set the NVM element to an erased state, prior to issuing signals for normal programming.

5. The memory of claim 1, wherein the processing element is further configured to issue control signals for the RECALL operation so that data recalled out of the non-volatile charge storage circuit into the volatile charge storage circuit is non-inverted.

6. The memory of claim 1, further comprising a clamping circuit, and wherein the processing element is further configured to issue control signals including a signal to the clamping circuit to electrically couple a second positive voltage supply line (VCCI) in the volatile charge storage circuit to the VSSI during the RECALL operation.

7. The memory of claim 6, further comprising a fifth transistor coupled between VCCT in the non-volatile charge storage circuit and ground (VGND), and wherein the processing element is further configured to issue control signals including a signal to the fifth transistor to electrically couple VCCT to VGND during the RECALL operation.

8. A memory comprising:

an array of non-volatile Static Random Access Memory (nvSRAM) cells, each nvSRAM cell comprising;

a volatile charge storage circuit; and

a non-volatile charge storage circuit comprising exactly one non-volatile memory (NVM) element, a first transistor through which a data true node (dt) in the volatile charge storage circuit is coupled to a first node of the NVM element, a second transistor through which a data complement node (dc) in the volatile charge storage circuit is coupled to the first node of the NVM element, and a third transistor through which a second node of the NVM element is coupled to a first positive voltage supply line (VCCT);

a fourth transistor coupled between a negative voltage supply line (VSSI) in the volatile charge storage circuit and a negative voltage supply (VSS); and

a processing element configured to issue control signals to each of the nvSRAM cells to execute a STORE operation and a RECALL operation,

wherein the control signals the processing element is configured to issue during the RECALL operation include a signal to the fourth transistor to electrically disconnect the VSSI from the VSS.

9. The memory of claim 8, wherein the control signals comprise signals for normal programming in which the first transistor is ON and the second and third transistors are OFF, and a plurality of pulses are applied to a gate node of the NVM element.

10. The memory of claim 8, wherein the processing element is further configured to issue control signals for the STORE operation comprising signals for bulk programming to set the NVM element to a programmed state, and signals for bulk erasing to set the NVM element to an erased state, prior to issuing signals for normal programming.

11. The memory of claim 8, wherein the processing element is configured to issue control signals for the RECALL operation so that data recalled out of the non-volatile charge storage circuit into the volatile charge storage circuit is non-inverted.

12. The memory of claim 8, further comprising a clamping circuit, and wherein the processing element is further configured to issue control signals including a signal to the clamping circuit to electrically couple a second positive voltage supply line (VCCI) in the volatile charge storage circuit to the VSSI during the RECALL operation.

13. The memory of claim 12, further comprising a fifth transistor coupled between VCCT in the non-volatile charge storage circuit and ground (VGND), and wherein the processing element is further configured to issue control signals including a signal to the fifth transistor to electrically couple VCCT to VGND during the RECALL operation.

14. A memory comprising:

an array of non-volatile Static Random Access Memory (nvSRAM) cells, each nvSRAM cell comprising;

a volatile charge storage circuit; and

a non-volatile charge storage circuit comprising a non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a first positive voltage supply line (VCCT); and

a processing element configured to issue control signals to each of the nvSRAM cells execute a STORE operation,

wherein during a normal program phase of the STORE operation in which the first transistor is ON and the second and third transistors are OFF, the processing element is configured to issue control signals including a plurality program pulses applied to a gate node of the NVM element, each program pulse having a pulse width substantially equal to a time between program pulses.

15. The memory of claim 14, wherein the processing element is further configured to issue control signals for the STORE operation comprising signals for bulk programming to set the NVM element to a programmed state, and signals for bulk erasing to set the NVM element to an erased state, prior to issuing signals for normal programming.

16. The memory of claim 14, wherein the processing element is further configured to issue control signals for a RECALL operation so that data recalled out of the non-volatile charge storage circuit into the volatile charge storage circuit is non-inverted.

17. The memory of claim 14, wherein further comprising a fourth transistor coupled between a negative voltage supply line (VSSI) in the volatile charge storage circuit and a negative voltage supply (VSS), and wherein the processing element is further configured to issue control signals for a RECALL operation including a signal to the fourth transistor to electrically disconnect the VSSI from the VSS during the RECALL operation.

18. The memory of claim 17, further comprising a clamping circuit, and wherein the processing element is further configured to issue control signals including a signal to the clamping circuit to electrically couple a second positive voltage supply line (VCCI) in the volatile charge storage circuit to the VSSI during the RECALL operation.

19. The memory of claim 18, further comprising a fifth transistor coupled between VCCT in the non-volatile charge storage circuit and ground (VGND), and wherein the processing element is further configured to issue control signals including a signal to the fifth transistor to electrically couple VCCT to VGND during the RECALL operation.