Medium defect management method for storage systems requiring an integrated controller

• US 9,997,251 B2
• Filed: 03/20/2016
• Issued: 06/12/2018
• Est. Priority Date: 03/26/2015
• Status: Active Grant

• Current Assignee: Michael Jones
• Original Assignee: Burlywood, LLC
• Inventors: Earhart, Tod R.
• Primary Examiner(s): Blair, April Y
• Assistant Examiner(s): Gandhi, Dipakkumar
• Application Number:
  US15/075,169
• Publication Number:
  US 20160283308A1
• Time in Patent Office: 814 Days
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A method of operating a storage controller is provided. The method includes receiving host data for storage within a storage system, the storage system configured as a plurality of sequentially numbered data blocks, each comprising a plurality of pages, storing the host data in a data buffer, and organizing the host data into storage data pages. The method also includes sequentially writing the storage data into page stripes, reading the storage data from the pages, and comparing the read storage data with the host data stored in the data buffer. The method further includes for each page of storage data that fails the comparison, rewriting the storage data for that page into a different page, and when at least some of the storage data within the storage system passes the comparison, transmitting a signal to the host.

Claims

1. A storage controller for a storage system, comprising:

a host interface, configured to receive host data for storage within the storage system;

a storage interface, configured to transmit storage data to the storage system using a sequential write/random read traffic model, the storage system configured to store data in a plurality of sequentially numbered data blocks, each data block comprising a plurality of pages wherein the sequential write/random read traffic model exclusively uses sequential writes and random reads; and

processing circuitry coupled with the host interface and the storage interface, configured to;

receive host data from a host, through the host interface, for storage within the storage system;

store the host data in a data buffer;

organize the host data into pages of storage data;

sequentially write the storage data into page stripes within the plurality of sequentially numbered data blocks through the storage interface;

read the storage data from the pages within the plurality of sequentially numbered data blocks through the storage interface;

compare the read storage data with the host data stored in the data buffer;

for each page of storage data that fails the comparison, rewrite the storage data for that page into a different page than the page in which it was previously stored; and

when at least some of the storage data within the storage system passes the comparison, transmit a signal to the host through the host interface.

2. The storage controller of claim 1, wherein the processing circuitry is further configured to:

store in a memory a quantity of pages failing the comparison for each data block; and

lock out data blocks where the quantity of pages failing the comparison exceeds a threshold.

3. The storage controller of claim 1, wherein the processing circuitry is further configured to:

store in a memory an identity of pages failing the comparison; and

lock out pages failing the comparison.

4. The storage controller of claim 1, wherein the processing circuitry is further configured to:

for each page failing the comparison, determine one or more portions of the page failing the comparison; and

lock out those one or more portions of the page failing the comparison.

5. The storage controller of claim 1, wherein reading the storage data from the pages within the plurality of sequentially numbered data blocks comprises:

a threshold read performed with narrower read margins than a normal read.

6. The storage controller of claim 1, wherein the processing circuitry is further configured to:

store metadata within each page comprising a sequence number and a page write count for the data stored within the page.

7. The storage controller of claim 1, wherein the signal transmitted to the host is a write acknowledge.

8. A method of operating a storage controller, comprising:

receiving host data from a host, through a host interface, for storage within a storage system, the storage system configured to store data in a plurality of sequentially numbered data blocks, each data block comprising a plurality of pages;

storing the host data in a data buffer;

organizing the host data into pages of storage data;

sequentially writing the storage data into page stripes within the plurality of sequentially numbered data blocks through a storage interface using a sequential write/random read traffic model, wherein the sequential write/random read traffic model exclusively uses sequential writes and random reads;

reading the storage data from the pages within the plurality of sequentially numbered data blocks through the storage interface;

comparing the read storage data with the host data stored in the data buffer;

for each page of storage data that fails the comparison, rewriting the storage data for that page into a different page than the page in which it was previously stored; and

when at least some of the storage data within the storage system passes the comparison, transmitting a signal to the host through the host interface.

9. The method of claim 8, further comprising:

storing in a memory a quantity of pages failing the comparison for each data block; and

locking out data blocks where the quantity of pages failing the comparison exceeds a threshold.

10. The method of claim 8, further comprising:

storing in a memory an identity of pages failing the comparison; and

locking out pages failing the comparison.

11. The method of claim 8, further comprising:

for each page failing the comparison, determining one or more portions of the page failing the comparison; and

locking out those one or more portions of the page failing the comparison.

12. The method of claim 8, wherein reading the storage data from the pages within the plurality of sequentially numbered data blocks comprises:

a threshold read performed with narrower read margins than a normal read.

13. The method of claim 8, further comprising:

storing metadata within each page comprising a sequence number and a page write count for the data stored within the page.

14. The method of claim 8, wherein the signal transmitted to the host is a write acknowledge.

15. One or more non-transitory computer-readable media having stored thereon program instructions to operate a storage controller for a storage system, wherein the program instructions, when executed by processing circuitry, direct the processing circuitry to at least:

receive host data from a host, through a host interface, for storage within the storage system, the storage system configured to store data in a plurality of sequentially numbered data blocks, each data block comprising a plurality of pages;

store the host data in a data buffer;

organize the host data into pages of storage data;

sequentially write the storage data into page stripes within the plurality of sequentially numbered data blocks through a storage interface configured to transmit the storage data to the storage system using a sequential write/random read traffic model, wherein the sequential write/random read traffic model exclusively uses sequential writes and random reads;

read the storage data from the pages within the plurality of sequentially numbered data blocks through the storage interface;

compare the read storage data with the host data stored in the data buffer;

for each page of storage data that fails the comparison, rewrite the storage data for that page into a different page than the page in which it was previously stored; and

when at least some of the storage data within the storage system passes the comparison, transmit a signal to the host through the host interface.

16. The one or more non-transitory computer-readable media of claim 15, wherein the program instructions further direct the processing circuitry to at least:

store in a memory a quantity of pages failing the comparison for each data block; and

lock out data blocks where the quantity of pages failing the comparison exceeds a threshold.

17. The one or more non-transitory computer-readable media of claim 15, wherein the program instructions further direct the processing circuitry to at least:

store in a memory an identity of pages failing the comparison; and

lock out pages failing the comparison.

18. The one or more non-transitory computer-readable media of claim 15, wherein the program instructions further direct the processing circuitry to at least:

for each page failing the comparison, determine one or more portions of the page failing the comparison; and

lock out those one or more portions of the page failing the comparison.

19. The one or more non-transitory computer-readable media of claim 15, wherein reading the storage data from the pages within the plurality of sequentially numbered data blocks comprises:

a threshold read performed with narrower read margins than a normal read.

20. The one or more non-transitory computer-readable media of claim 15, wherein the program instructions further direct the processing circuitry to at least:

store metadata within each page comprising a sequence number and a page write count for the data stored within the page.