Non-volatile memory array with memory gate line and source line scrambling
First Claim
1. A memory device, comprising:
- a memory array arranged in rows and columns, including,at least four non-volatile memory (NVM) cells coupled in a same column of the memory array, wherein each NVM cell includes a memory gate, and wherein first and second NVM cells of the at least four NVM cells share a first source line and third and fourth NVM cells share a second source line, wherein the first and second source lines are adjacent to one another,wherein the memory gates of the first and second NVM cells are not electrically coupled with one another, wherein the first and second source lines are not electrically coupled with one another, and wherein each of the first and second source lines is physically connected with at least one source line of the same column that is not the first and second source lines.
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Accused Products
Abstract
A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.
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Citations
21 Claims
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1. A memory device, comprising:
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a memory array arranged in rows and columns, including, at least four non-volatile memory (NVM) cells coupled in a same column of the memory array, wherein each NVM cell includes a memory gate, and wherein first and second NVM cells of the at least four NVM cells share a first source line and third and fourth NVM cells share a second source line, wherein the first and second source lines are adjacent to one another, wherein the memory gates of the first and second NVM cells are not electrically coupled with one another, wherein the first and second source lines are not electrically coupled with one another, and wherein each of the first and second source lines is physically connected with at least one source line of the same column that is not the first and second source lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory array, comprising:
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non-volatile memory (NVM) cells, each including a memory gate and a select gate, arranged in rows and columns, wherein, two adjacent NVM cells of a same column that share a source region form an NVM pair, wherein the source region is disposed between memory gates of the two adjacent NVM cells, and wherein multiple NVM pairs are coupled to one another in the same column, at least two memory gates of NVM cells of a same row share a memory gate line, at least two source regions of NVM cells of the same row share a source line; and source line connection routing configured to connect multiple source lines physically and electrically to form multiple source line groups, wherein the multiple source lines in a same source line group are not physically adjacent to one another. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method, comprising:
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providing a non-volatile memory (NVM) array, wherein the non-volatile memory array includes at least four non-volatile memory (NVM) cells coupled in a same column of the NVM array, wherein each NVM cell includes a memory gate and a select gate, wherein first and second NVM cells of the at least four NVM cells share a first source line, and third and fourth NVM cells share a second source line, and wherein the first and second source lines are each physically connected with at least another source line that is not physically adjacent to the first and second source lines respectively; coupling a high select voltage to a first select gate to select the first memory cell for a program operation; coupling a low select voltage to a second select gate to unselect the second memory cell for the program operation; coupling a high program voltage to the first memory gate and a low inhibit voltage to the second memory gate; and coupling two different source voltages to the first source line and the second source line from two different source line driver circuits, respectively. - View Dependent Claims (21)
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Specification