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Non-volatile memory array with memory gate line and source line scrambling

  • US 9,997,253 B1
  • Filed: 03/28/2017
  • Issued: 06/12/2018
  • Est. Priority Date: 12/08/2016
  • Status: Active Grant
First Claim
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1. A memory device, comprising:

  • a memory array arranged in rows and columns, including,at least four non-volatile memory (NVM) cells coupled in a same column of the memory array, wherein each NVM cell includes a memory gate, and wherein first and second NVM cells of the at least four NVM cells share a first source line and third and fourth NVM cells share a second source line, wherein the first and second source lines are adjacent to one another,wherein the memory gates of the first and second NVM cells are not electrically coupled with one another, wherein the first and second source lines are not electrically coupled with one another, and wherein each of the first and second source lines is physically connected with at least one source line of the same column that is not the first and second source lines.

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