Lift off process for chip scale package solid state devices on engineered substrate

• US 9,997,391 B2
• Filed: 10/07/2016
• Issued: 06/12/2018
• Est. Priority Date: 10/19/2015
• Status: Active Grant

• Current Assignee: Qromis, Inc.
• Original Assignee: Qromis, Inc.
• Inventors: Odnoblyudov, Vladimir, Basceri, Cem
• Primary Examiner(s): Ahmed, Selim
• Assistant Examiner(s): CLINTON, EVAN GARRETT
• Application Number:
  US15/288,506
• Publication Number:
  US 20170110314A1
• Time in Patent Office: 613 Days
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/7813 leaving a reusable substrate, e.g. epitaxial lift off
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 33/00 Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof H10K50/00 takes precedence; devices consisting of a plurality of semiconductor components formed in or on a common substrate and including semiconductor components having potential barriers, specially adapted for light emission H01L27/15; semiconductor lasers H01S5/00
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body
• CPC Class Codes: H01L 33/50 Wavelength conversion elements

Abstract

A method of processing an engineered substrate structure includes providing an engineered substrate structure including a polycrystalline substrate and an engineered layer encapsulating the polycrystalline substrate, forming a sacrificial layer coupled to the engineered layer, joining a solid state device structure to the sacrificial layer, forming one or more channels in the solid state device structure by removing one or more portions of the solid state device structure to expose one or more portions of the sacrificial layer, flowing an etching chemical through the one or more channels to the one or more exposed portions of the sacrificial layer, and dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer, thereby separating the engineered substrate structure from the solid state device structure.

Claims

1. A method of processing an engineered substrate structure, the method comprising:

providing an engineered substrate structure including;

a polycrystalline substrate; and

an engineered layer encapsulating the polycrystalline substrate;

forming a sacrificial layer coupled to the engineered layer;

forming a solid state device structure coupled to the sacrificial layer by;

forming a bonding layer coupled to the sacrificial layer;

forming a substantially single crystalline silicon layer coupled to the bonding layer;

epitaxially growing a gallium nitride (GaN) layer on the substantially single crystalline silicon layer;

forming an N—

GaN layer coupled to the GaN layer by epitaxial growth;

forming a GaN-based active layer coupled to the N—

GaN layer by epitaxial growth; and

forming a P—

GaN layer coupled to the GaN-based active layer by epitaxial growth;

forming a molding support on the solid state device structure;

forming one or more channels in the solid state device structure by removing one or more portions of the solid state device structure to expose one or more portions of the sacrificial layer;

flowing an etching chemical through the one or more channels to the one or more exposed portions of the sacrificial layer; and

dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer, thereby separating the engineered substrate structure from the solid state device structure.

2. The method of claim 1 wherein the sacrificial layer comprises one of titanium (Ti), vanadium (V), chromium (Cr), tantalum (Ta), tungsten (W), rhenium (Re), silicon oxide, silicon nitride, silicon oxinitride, or a combination thereof.

3. The method of claim 1 wherein the etching chemical comprises hydrofluoric acid (HF) or sulfuric acid (H₂SO₄).

4. The method of claim 1 wherein the polycrystalline substrate comprises one of polycrystalline aluminum gallium nitride (AlGaN), polycrystalline gallium nitride (GaN), polycrystalline aluminum nitride (AlN), silicon carbide (SiC), or a combination thereof.

5. The method of claim 1 wherein each of the one or more channels passes through the molding support, the GaN layer, the substantially single crystalline silicon layer, and the bonding layer.

6. A method of processing an engineered substrate structure, the method comprising:

providing an engineered substrate structure including;

a polycrystalline substrate; and

an engineered layer encapsulating the polycrystalline substrate;

forming a sacrificial layer coupled to the engineered layer, the sacrificial layer having an exposed periphery;

forming a solid state device structure coupled to the sacrificial layer by;

forming a bonding layer coupled to the sacrificial layer;

forming a substantially single crystalline silicon layer coupled to the bonding layer;

forming a gallium nitride (GaN) layer coupled to the substantially single crystalline silicon layer; and

forming one or more GaN-based devices coupled to the GaN layer;

forming a molding support on the solid state device structure;

applying an etching chemical to the exposed periphery of the sacrificial layer; and

dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer, thereby separating the engineered substrate structure from the solid state device structure.

7. The method of claim 6 wherein the sacrificial layer comprises one of titanium (Ti), vanadium (V), chromium (Cr), tantalum (Ta), tungsten (W), rhenium (Re), silicon oxide, silicon nitride, silicon oxinitride, or a combination thereof.

8. The method of claim 6 wherein the etching chemical comprises hydrofluoric acid (HF) or sulfuric acid (H₂SO₄).

9. The method of claim 6 wherein the polycrystalline substrate comprises one of polycrystalline aluminum gallium nitride (AlGaN), polycrystalline gallium nitride (GaN), polycrystalline aluminum nitride (AlN), silicon carbide (SiC), or a combination thereof.