Formation of metal resistor and e-fuse

• US 9,997,411 B2
• Filed: 08/27/2015
• Issued: 06/12/2018
• Est. Priority Date: 05/06/2014
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Tran, Cung, Alptekin, Emre, Sardesai, Viraj, Vega, Reinaldo
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US14/837,580
• Publication Number:
  US 20150364419A1
• Time in Patent Office: 1,020 Days
• Field of Search: 438382
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823443 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/24 with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66515 using self aligned selective metal deposition simultaneously on the gate and on source or drain
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Embodiments of present disclosure provide methods of forming a resistor. One such method can include forming a first transistor structure and a second transistor structure on a semiconductor substrate, wherein the first transistor structure includes a dummy gate thereon; forming a mask on the first transistor structure; forming a metal gate on the second transistor structure; removing the mask, after the forming of the metal gate, to expose the first transistor structure; and siliciding a top portion of the dummy gate of the first transistor structure to yield a resistor.

Claims

1. A method comprising:

forming a first transistor structure and a pair of second transistor structures on a semiconductor substrate, wherein the first transistor structure includes a dummy gate thereon, wherein a shared silicide region is positioned laterally between the pair of second transistor structures and directly contacts both of the pair of second transistor structures, and wherein the first transistor structure is laterally separated from the pair of second transistor structures;

forming a mask only on the first transistor structure, the pair of second transistor structures remaining uncovered by the mask;

forming a metal gate on each of the pair of second transistor structures to yield a set of transistors;

forming a recess in each metal gate, before removal of the mask from the first transistor structure;

depositing a dielectric material in the recess in each metal gate and over the mask on the first transistor structure, wherein an entire top portion of each metal gate in the recess is covered by the dielectric material;

removing the dielectric material and the mask to expose the first transistor structure, without removing the dielectric material within the recess in each metal gate; and

siliciding a top portion of the dummy gate of the first transistor structure to yield a resistor.

2. The method of claim 1, further comprising:

forming a dielectric layer on the silicided top portion of the dummy gate of the first transistor structure; and

forming at least two a contacts within the dielectric layer and in contact with the resistor.

3. The method of claim 1, wherein the first transistor structure has a same structure as each of the pair of second transistor structures.

4. The method of claim 1, wherein the removing of the dielectric material and the mask to expose the first transistor structure includes applying a chemical mechanical polishing (CMP) process.

5. The method of claim 1, further comprising siliciding a source/drain region of the first transistor structure.

6. A method comprising:

forming a first transistor structure and a pair of second transistor structures on a semiconductor substrate, wherein each of the first transistor structure and the pair of second transistor structures includes a dummy gate thereon, wherein a shared silicide region is positioned laterally between the pair of second transistor structures and directly contacts both of the pair of second transistor structures, wherein the first transistor structure is laterally separated from the pair of second transistor structures;

forming a mask only on the first transistor structure, the pair of second transistor structures remaining uncovered by the mask;

replacing the dummy gate of the pair of second transistor structures with a metal gate to form a set of transistors;

forming a recess in each metal gate, before removal of the mask from the first transistor structure;

depositing a dielectric material in the recess in each metal gate and over the mask on the first transistor structure, wherein an entire top portion of each metal gate in the recess is covered by the dielectric material;

removing the dielectric material and the mask to expose the first transistor structure, without removing the dielectric material within the recess in each metal gate; and

siliciding a top portion of the dummy gate of the first transistor structure to form a resistor.

7. The method of claim 6, further comprising:

forming a dielectric layer on the silicided top portion of the dummy gate of the first transistor structure; and

forming at least two contacts within the dielectric layer and in contact with the resistor.

8. The method of claim 6, wherein the removing of the dielectric material and the mask to expose the first transistor structure includes applying a chemical mechanical polishing (CMP) process.

9. The method of claim 6, wherein the dielectric material and the mask each include a same dielectric material.

10. The method of claim 6, further comprising siliciding a source/drain region of the first transistor structure.

11. The method of claim 10, wherein the removing of the dielectric material and the mask to expose the first transistor structure includes applying a chemical mechanical polishing (CMP) process.

12. The method of claim 10, wherein the dielectric material and the mask include a same dielectric material.

13. A method comprising:

forming a first and a pair of second transistor structures on a semiconductor substrate, wherein each of the first transistor structure and each of the pair of second transistor structures includes;

a source/drain region positioned within the semiconductor substrate, and

a dummy gate positioned over the source/drain region,

wherein a shared silicide region is positioned laterally between the pair of second transistor structures and directly contacts both of the pair of second transistor structures, wherein the first transistor structure is laterally separated from the pair of second transistor structures;

forming a mask only on the first transistor structure, the pair of second transistor structures remaining uncovered by the mask;

forming a replacement metal gate on each of the pair of second transistor structures to yield a set of transistors;

forming a recess in each metal gate, before removal of the mask from the first transistor structure;

depositing a dielectric material in the recess in each metal gate and over the mask on the first transistor structure, wherein an entire top portion of each metal gate in the recess is covered by the dielectric material;

removing the dielectric material and the mask to expose the first transistor structure, without removing the dielectric material within the recess in each metal gate; and

siliciding a top portion of the dummy gate of the first transistor structure to form a resistor.

14. The method of claim 13, further comprising:

forming a dielectric layer on the silicided top portion of the dummy gate of the first transistor structure; and

forming at least two contacts within the dielectric layer and in contact with the resistor.