Stacked vertical devices

• US 9,997,413 B1
• Filed: 03/22/2017
• Issued: 06/12/2018
• Est. Priority Date: 03/22/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Leobandung, Effendi
• Primary Examiner(s): Shingleton, Michael
• Application Number:
  US15/466,168
• Time in Patent Office: 447 Days
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor structure containing a plurality of stacked vertical field effect transistor (FETs) is provided. After forming a first vertical FET of a first conductivity type at a lower portion of a semiconductor fin, a second vertical FET of a second conductivity type is formed on top of the first vertical FET. The second conductivity type can be opposite to, or the same as, the first conductivity type. A source/drain region of the first vertical FET is electrically connected to a source/drain region of the second vertical FET by a conductive strip structure.

Claims

1. A semiconductor structure comprising:

a first vertical field effect transistor (FET) of a first conductivity type, wherein the first vertical FET comprises;

a first doped epitaxial semiconductor region along sidewalls of a first doped fin region of a semiconductor fin that extends upwards from a semiconductor substrate portion,

a first gate structure along sidewalls of a first channel region of the semiconductor fin that is located above the first doped fin region, and

a second doped epitaxial semiconductor region along sidewalls of a second doped fin region of the semiconductor fin that is located above the first channel region;

a second vertical FET of a second conductivity type stacked on the first vertical FET, wherein the second vertical FET comprises;

a third doped epitaxial semiconductor region along sidewalls of a third doped fin region of the semiconductor fin that is located atop the second doped fin region,

a second gate structure along sidewalls of a second channel region of the semiconductor fin that is located above the third doped fin region, and

a fourth doped epitaxial semiconductor region along sidewalls a fourth doped fin region of the semiconductor that is located above the second channel region; and

a conductive strap structure laterally contacting the second doped epitaxial semiconductor region and the third doped epitaxial semiconductor region.

2. The semiconductor structure of claim 1, wherein the conductive strap structure laterally contacts an entirety of the third doped epitaxial semiconductor region and an upper portion of the second doped epitaxial semiconductor region.

3. The semiconductor structure of claim 1, further comprising a first insulating spacer separating the first doped epitaxial semiconductor region from the first gate structure.

4. The semiconductor structure of claim 3, further comprising a second insulating spacer separating the first gate structure from the second doped epitaxial semiconductor region.

5. The semiconductor structure of claim 4, further comprising a third insulating spacer located over the second insulating spacer and laterally contacting a portion of the second doped epitaxial semiconductor region that is not laterally contacted by the conductive strap structure.

6. The semiconductor structure of claim 5, wherein the conductive strap structure vertically contacts the third insulating spacer.

7. The semiconductor structure of claim 6, further comprising a fourth insulating spacer separating the third doped epitaxial semiconductor region and the conductive strap structure from the second gate structure.

8. The semiconductor structure of claim 6, further comprising a fifth insulating spacer separating the second gate structure from the fourth doped epitaxial semiconductor region.

9. The semiconductor structure of claim 1, wherein the conductive strap structure comprises a silicide or germicide.

10. The semiconductor structure of claim 1, wherein the second conductivity type is opposite to, or the same as, the first conductivity type.

11. The semiconductor structure of claim 1, wherein the fourth doped epitaxial semiconductor region contacts the sidewalls and a topmost surface of the fourth doped fin region.