Apparatus and method of three dimensional conductive lines

• US 9,997,436 B2
• Filed: 12/15/2016
• Issued: 06/12/2018
• Est. Priority Date: 11/12/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chih-Yu, Lin, Kao-Cheng, Wang, Li-Wen, Chen, Yen-Huei
• Primary Examiner(s): Sefer, A.
• Application Number:
  US15/379,537
• Publication Number:
  US 20170098596A1
• Time in Patent Office: 544 Days
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 99/10 Memory cells having a cross-point geometry

Abstract

An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

Claims

1. An inter-tier memory column, comprising:

a first segment disposed within a first tier of a three-dimensional integrated circuit (3D IC), the first segment comprising a first bit line disposed on a first side of a longitudinal axis, a first bit line bar disposed on a second side of the longitudinal axis, and a first plurality of memory cells, said first plurality of memory cells electrically connected to said first bit line and said first bit line bar;

a second segment disposed within a second tier of the 3D IC, comprising a second bit line disposed on the second side of the longitudinal axis, a second bit line bar disposed on the first side of the longitudinal axis, and a second plurality of memory cells, said second plurality of memory cells electrically connected to said second bit line and said second bit line bar; and

wherein said first bit line is electrically connected to said second bit line by a conductive member extending continuously from said first bit line to said second bit line, and said first bit line bar is electrically connected to said second bit line bar by a conductive member extending continuously from said first bit line bar to said second bit line bar.

2. The inter-tier memory column of claim 1, wherein said first segment and said second segment are aligned parallel to each other.

3. The inter-tier memory column of claim 1, further comprising:

an inter-tier word line connected across said first segment and said second segment.

4. The inter-tier memory column of claim 1,

wherein said first bit line comprises a first bit line part and a horizontally offset second bit line part, said second bit line comprises a third bit line part and a perpendicular fourth bit line part;

and

wherein said horizontally offset second bit line part and said perpendicular fourth bit line part are connected by a vertical bit line.

5. The inter-tier memory column of claim 4,

wherein said first bit line bar comprises a first bit line bar part and a horizontally offset second bit line bar part, said second bit line bar comprises a third bit line bar part and a perpendicular fourth bit line bar part;

and

wherein said horizontally offset second bit line bar part and said perpendicular fourth bit line bar part are connected by a vertical bit line.

6. The inter-tier memory column of claim 1, further comprising:

a third segment disposed within a first tier of the 3D IC, the third segment comprising a third bit line disposed on the first side of a longitudinal axis, a third bit line bar disposed on the second side of the longitudinal axis, and a third plurality of memory cells, said third plurality of memory cells electrically connected to said third bit line and third first bit line bar; and

a fourth segment disposed within a second tier of the 3D IC, comprising a fourth bit line disposed on the second side of the longitudinal axis, a fourth bit line bar disposed on the first side of the longitudinal axis, and a fourth plurality of memory cells, said fourth plurality of memory cells electrically connected to said fourth bit line and said fourth bit line bar.

7. The inter-tier memory column of claim 6, wherein said third bit line is electrically connected to said fourth bit line by a conductive member extending continuously from said third bit line to said fourth bit line, and said third bit line bar is electrically connected to said fourth bit line bar by a conductive member extending continuously from said third bit line bar to said fourth bit line bar.

8. The inter-tier memory column of claim 6 wherein said third segment is disposed above said second segment and said fourth segment is disposed below said first segment.

9. An inter-tier memory column, comprising:

a first segment disposed within a first tier of a three-dimensional integrated circuit (3D IC), the first segment comprising a first bit line disposed on a first side of a longitudinal axis, a first bit line bar disposed on a second side of the longitudinal axis, and a first plurality of memory cells, said first plurality of memory cells electrically connected to said first bit line and said first bit line bar;

a second segment disposed within a second tier of the 3D IC, comprising a second bit line disposed on the second side of the longitudinal axis, a second bit line bar disposed on the first side of the longitudinal axis, and a second plurality of memory cells, said second plurality of memory cells electrically connected to said second bit line and said second bit line bar;

wherein said first bit line comprises a horizontally offset bit line part which extends parallel to the longitudinal axis and said second bit line comprises a perpendicular bit line part extending perpendicular to the longitudinal axis; and

wherein said horizontally offset bit line part is connected to said perpendicular bit line part by a first vertical bit line.

10. The inter-tier memory column of claim 9,

wherein said first bit line bar comprises a first bit line bar part and a horizontally offset second bit line bar part, said second bit line bar comprises a third bit line bar part and a perpendicular fourth bit line bar part;

and

wherein said horizontally offset second bit line bar part and said perpendicular fourth bit line bar part are connected by a second vertical bit line.

11. The inter-tier memory column of claim 10 wherein said first vertical bit line extends continuously from said horizontally offset bit line part to said perpendicular bit line part.

12. The inter-tier memory column of claim 11 wherein said second vertical bit line extends continuously from said horizontally offset second bit line bar part to said perpendicular fourth bit line bar part.

13. The inter-tier memory column of claim 9 further comprising an inter-tier conductive line coupled between said first bit line and said second bit line.

14. The inter-tier memory column of claim 9 further comprising a first horizontal extender coupling said first bit line and said horizontally offset bit line part.

15. The inter-tier memory column of claim 14 further comprising a second horizontal extender coupling said first bit line bar part and said horizontally offset second bit line bar part.

16. A method of forming an inter-tier memory column, comprising:

forming a first segment in a first tier of a three-dimensional integrated circuit (3D IC), said first segment comprising a first bit line disposed on a first side of a longitudinal axis, a first bit line bar disposed on a second side of the longitudinal axis, and a first plurality of memory cells, said first plurality of memory cells electrically connected to said first bit line and said first bit line bar, wherein said first bit line comprises a horizontally offset bit line part which extends parallel to the longitudinal axis;

forming a second segment disposed within a second tier of the 3D IC, the second segment comprising a second bit line disposed on the second side of the longitudinal axis, a second bit line bar disposed on the first side of the longitudinal axis, and a second plurality of memory cells, said second plurality of memory cells electrically connected to said second bit line and said second bit line bar, wherein said second bit line comprises a perpendicular bit line part extending perpendicular to the longitudinal axis; and

connecting said horizontally offset bit line part to said perpendicular bit line part with a first vertical bit line.

17. The method of claim 16 wherein said first vertical bit line extends continuously from said horizontally offset bit line part to said perpendicular bit line part.

18. The method of claim 16 further comprising connecting said first bit line bar to said second bit line bar with a continuously extending second vertical bit line.

19. The method of claim 18 wherein said first bit line bar comprises a first bit line bar part and a horizontally offset second bit line bar part, said second bit line bar comprises a third bit line bar part and a perpendicular fourth bit line bar part.

20. The method of claim 16 further comprising forming an inter-tier word line which connects at least one bit line of the first tier and at least one bit line of the second tier.