Protection layer for adhesive material at wafer edge

• US 9,997,440 B2
• Filed: 04/17/2013
• Issued: 06/12/2018
• Est. Priority Date: 09/14/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiou, Wen-Chih, Wu, Weng-Jin, Shue, Shau-Lin
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): BOYLE, ABBIGALE A
• Application Number:
  US13/864,676
• Publication Number:
  US 20130228920A1
• Time in Patent Office: 1,882 Days
• Field of Search: None
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A three-dimensional integrated circuit (3DIC) including a first substrate having a first surface and a second surface opposite to the first surface and a second substrate attached to the first surface of the first substrate. The 3DIC further includes an interconnect between attached to the first surface of the first substrate and the second substrate and a plurality of through vias formed in the first substrate and electrically coupled to the interconnect. The 3DIC further includes a protection layer over the second surface of the first substrate, wherein each of the plurality of through vias protrudes through the protection layer and a plurality of dies, each die of the plurality of dies attached to at least one through via of the plurality of through vias.

Claims

1. A three-dimensional integrated circuit, comprising:

a first substrate having a first surface and a second surface opposite to the first surface, wherein the first substrate has a thickness ranging from about 5 micrometers (μ

m) to about 50 μ

m;

a second substrate attached to the first surface of the first substrate;

an interconnect between attached to the first surface of the first substrate and the second substrate;

a plurality of through vias formed in the first substrate and electrically coupled to the interconnect;

a protection layer over the second surface of the first substrate, wherein each of the plurality of through vias protrudes through the protection layer; and

a plurality of dies, each die of the plurality of dies attached to at least one through via of the plurality of through vias.

2. The 3DIC of claim 1, wherein the protection layer comprises at least one of an oxide film, a nitride film, a carbide film, a polymer-based material, a resin-based material, polyimide, or a spin-on material.

3. The 3DIC of claim 1, further comprising at least one conductive structure configured to attach each of the plurality of dies to at least one of the plurality of through vias.

4. The 3DIC of claim 3, wherein the at least one conductive structure comprises at least one solder bump or at least one copper bump.

5. The 3DIC of claim 3, wherein the at least one conductive structure comprises a redistribution layer.

6. The 3DIC of claim 1, wherein each die of the plurality of dies comprises at least one of a memory chip, a radio frequency chip, or a logic chip.

7. The 3DIC of claim 1, wherein the second substrate comprises at least one of glass, metal, ceramic, or polymer.

8. The 3DIC of claim 1, wherein each through via of the plurality of through vias are electrically coupled to a bond pad on the first surface of the first substrate and to a die of the plurality of dies on a second surface of the first substrate.

9. The 3DIC of claim 1, wherein the second substrate is an integrated circuit card, and the second substrate is attached to the first substrate through an anisotropically conductive connection film.

10. A three-dimensional integrated circuit, comprising:

a first substrate having a first surface and a second surface opposite to the first surface, wherein the first substrate has a thickness ranging from about 5 micrometers (μ

m) to about 50 μ

m;

a second substrate attached to the first surface of the first substrate;

a plurality of bond pads attached to the first surface of the first substrate;

a plurality of through vias formed in the first substrate and electrically coupled to the bond pads;

a protection layer over the second surface of the first substrate, wherein each of the plurality of through vias is free of the protection layer; and

a plurality of dies, each die of the plurality of dies attached to at least one through via of the plurality of through vias.

11. The 3DIC of claim 10, wherein the protection layer comprises at least one of an oxide film, a nitride film, a carbide film, a polymer-based material, a resin-based material, polyimide, or a spin-on material.

12. The 3DIC of claim 10, further comprising at least one conductive structure configured to attach each of the plurality of dies to at least one of the plurality of through vias.

13. The 3DIC of claim 12, wherein the at least one conductive structure comprises at least one solder bump or at least one copper bump.

14. The 3DIC of claim 12, wherein the at least one conductive structure comprises a redistribution layer.

15. The 3DIC of claim 10, wherein each die of the plurality of dies comprises at least one of a memory chip, a radio frequency chip, or a logic chip.

16. The 3DIC of claim 10, wherein the second substrate comprises at least one of glass, metal, ceramic, or polymer.

17. The 3DIC of claim 10, wherein the second substrate is an integrated circuit card, and the second substrate is attached to the first substrate through an anisotropically conductive connection film.

18. A three-dimensional integrated circuit, comprising:

a substrate having a first surface and a second surface opposite to the first surface, wherein the first substrate has a thickness ranging from about 5 micrometers (μ

m) to about 50 μ

m;

an integrated circuit card attached to the first surface of the substrate through an anisotropically conductive connection film;

a plurality of bond pads attached to the first surface of the substrate;

a plurality of through vias formed in the substrate and electrically coupled to the bond pads;

a protection layer over the second surface of the substrate, wherein each of the plurality of through vias extends through the protection layer; and

a plurality of dies, each die of the plurality of dies attached to at least one through via of the plurality of through vias.