Device architecture and method for precision enhancement of vertical semiconductor devices

• US 9,997,455 B2
• Filed: 03/06/2017
• Issued: 06/12/2018
• Est. Priority Date: 11/26/2012
• Status: Expired due to Fees

• Current Assignee: D3 Semiconductor LLC (D3 Semiconductor Asia Sdn. Bhd.)
• Original Assignee: D3 Semiconductor LLC (D3 Semiconductor Asia Sdn. Bhd.)
• Inventors: Harrington, III, Thomas E.
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US15/451,074
• Publication Number:
  US 20170179024A1
• Time in Patent Office: 463 Days
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/5258 the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a direct impact on the performance achievement and power efficiency of the systems in which these devices are used. Imprecise vertical device specifications cause system builders to either screen incoming devices for their required specification targets or to design their system with lower performance or lower efficiency than desired. Disclosed is an architecture and method for achieving a desired target specification for a vertical semiconductor device. Precise trimming of threshold voltage improves targeting of both on-resistance and switching time. Precise trimming of gate resistance also improves targeting of switching time. Precise trimming of a device'"'"'s effective width improves targeting of both on-resistance and current-carrying capability. Device parametrics are trimmed to improve a single device, or a parametric specification is targeted to match specifications on two or more devices.

Claims

1. A trimmable vertical semiconductor device, comprising:

a first vertical semiconductor device having a first gate terminal, a first source terminal and a first drain terminal;

a second semiconductor device having a second gate terminal, a second source terminal and a second drain terminal;

the first vertical semiconductor device connected in parallel to the second semiconductor device;

a first isolation fuse, connected between the first gate terminal and the second gate terminal; and

,

the first isolation fuse including a first terminal and a second terminal, the first terminal connected to the first gate terminal and the second terminal connected to the second gate terminal and connected to a second isolation fuse.

2. The trimmable vertical semiconductor device of claim 1, further comprising:

an activation fuse, connected between the first source terminal and the second gate terminal; and

,

wherein the second semiconductor device is a second vertical semiconductor device.

3. The trimmable vertical semiconductor device of claim 2, further comprising:

a set of third vertical semiconductor devices.

4. The trimmable vertical semiconductor device of claim 3, further comprising:

each of the set of third vertical semiconductor devices having a third gate terminal, a third source terminal and a third drain terminal.

5. The trimmable vertical semiconductor device of claim 4, further comprising:

each of the set of third vertical semiconductor devices connected in parallel to the first vertical semiconductor device.

6. The trimmable vertical semiconductor device of claim 5, further comprising:

a set of second isolation fuses, each of the set of second isolation fuses connected between the first gate terminal and each third gate terminal of the set of third vertical semiconductor devices; and

,

the set of second isolation fuses including the second isolation fuse.

7. The trimmable vertical semiconductor device of claim 6, further comprising:

a set of second activation fuses, each of the set of second activation fuses connected between the first source terminal and each third gate terminal of the set of third vertical semiconductor devices.

8. The trimmable vertical semiconductor device of claim 7, further comprising:

a set of first resistors.

9. The trimmable vertical semiconductor device of claim 8, further comprising:

each resistor, of the set of first resistors, connected between each of the set of second isolation fuses and each third gate terminal of the set of third vertical semiconductor devices.

10. The trimmable vertical semiconductor device of claim 2, further comprising:

a first resistor, connected between the activation fuse and the second gate terminal.

11. The trimmable vertical semiconductor device of claim 2, wherein the first vertical semiconductor device is a MOSFET device and the second vertical semiconductor device is a MOSFET device.

12. The trimmable vertical semiconductor device of claim 2, wherein the first vertical semiconductor device is an IGBT device and the second vertical semiconductor device is an IGBT device.

13. The trimmable vertical semiconductor device of claim 2, wherein the first vertical semiconductor device is a VDMOS and the second vertical semiconductor device is a VDMOS device.