Optically-masked microelectronic packages and methods for the fabrication thereof

• US 9,997,492 B2
• Filed: 11/21/2013
• Issued: 06/12/2018
• Est. Priority Date: 11/21/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Yap, Weng F., Hayes, Scott M., Magnus, Alan J.
• Primary Examiner(s): Vu, David
• Application Number:
  US14/086,745
• Publication Number:
  US 20150137381A1
• Time in Patent Office: 1,664 Days
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

Microelectronic packages and methods for fabricating microelectronic packages having optical mask layers are provided. In one embodiment, the method includes building redistribution layers over the frontside of a semiconductor die. The redistribution layers includes a body of dielectric material in which a plurality of interconnect lines are formed. An optical mask layer is formed over the frontside of the semiconductor die and at least a portion of the redistribution layers. The optical mask layer has an opacity greater than the opacity of the body of dielectric material and blocks or obscures visual observation of an interior portion of the microelectronic package through the redistribution layers.

Claims

1. A method for fabricating an optically-masked microelectronic package, comprising:

building redistribution layers over the frontside of a semiconductor die, the redistribution layers comprising a body of dielectric material in which a plurality of interconnect lines are formed;

forming an optical mask layer overlying the frontside of the semiconductor die and at least a portion of the redistribution layers, the optical mask layer having an opacity greater than the opacity of the body of dielectric material and blocking or obscuring visual observation of an interior portion of the microelectronic package through the redistribution layers; and

producing a contact array before or after formation of the optical mask layer electrically coupled to the plurality of interconnect lines, at least some of the contacts included within the contact array projecting through openings in the optical mask layer, the openings sized such that a circumferential clearance having a predetermined gap width is formed around each contact projecting through the optical mask layer.

2. The method of claim 1 wherein the redistribution layers are built over the frontside of a molded panel in which the semiconductor die and a plurality of other semiconductor die are embedded, the frontside of the semiconductor die exposed through the frontside of the molded panel;

and

wherein the method further comprises singulating the molded panel after forming the optical mask layer to produce a plurality of microelectronic packages, each microelectronic package containing a semiconductor die embedded within a molded packaged body.

3. The method of claim 2 wherein forming an optical mask layer comprises forming the optical mask layer over the outermost redistribution layer prior to singulation of the molded panel.

4. The method of claim 1 wherein forming an optical mask layer comprises forming the optical mask over selected regions of the semiconductor die, while leaving other regions of the semiconductor die uncovered by the optical mask layer.

5. The method of claim 1 wherein forming an optical mask layer comprises forming the optical mask to have a repeating geometric pattern.

6. The method of claim 5 wherein the repeating geometric pattern is selected from the group consisting of a checkerboard pattern, a zigzag pattern, a lattice pattern, a wave pattern, and a swirl pattern.

7. The method of claim 1 wherein the redistribution layers comprise an outer solder mask layer overlying the plurality of interconnect lines and making-up a portion of the body of dielectric material;

wherein the method further comprises creating openings in the outer solder mask layer exposing selected regions of the interconnect lines therethrough; and

wherein forming an optical mask layer comprises forming the optical mask layer over the redistribution layers after creating openings in the outer solder mask layer.

8. The method of claim 7 wherein the optical mask layer is deposited directly on or adhered directly to the outer solder mask layer.

9. The method of claim 7 wherein forming an optical mask layer comprises:

depositing a blank optical mask layer over the outer solder mask layer and into the openings to cover the selected regions of the interconnect lines; and

removing portions of the blank optical mask layer covering the selected regions of the interconnect lines to define the optical mask layer.

10. The method of claim 9 wherein depositing a blank optical mask layer comprises sputter depositing a metal film layer over outer solder mask layer and into the openings to cover the selected regions of the interconnect lines.

11. The method of claim 1 further comprising forming a sealant layer over the optical mask layer, the sealant layer composed of a different material than is the optical mask layer.

12. The method of claim 11 wherein the optical mask layer is composed of a metallic material, and wherein the sealant layer is composed of a non-conductive epoxy.

13. The method of claim 1 wherein the contact array is produced such that each contact that projects through an opening in the optical mask layer has a maximum diameter less than the diameter of the opening.

14. The method of claim 1 further comprising applying a sealant layer over the optical mask layer, the solid sealant layer applied in a solid state as a freestanding film bonded to an outer surface of the optical mask layer.

15. A method for fabricating an optically-masked microelectronic package, comprising:

building redistribution layers over the frontside of a semiconductor die, the redistribution layers comprising a body of dielectric material, an outer solder mask layer included in the body of dielectric material, and a plurality of interconnect lines formed in the body of dielectric material;

creating openings in the outer solder mask layer exposing selected regions of the interconnect lines; and

forming an optical mask layer over the redistribution layers after creating the openings in the outer solder mask layer, the optical mask layer having an opacity greater than the opacity of the body of dielectric material and blocking or obscuring visual observation of an interior portion of the microelectronic package through the redistribution layers;

wherein forming the optical mask layer comprising;

forming sacrificial plugs in the openings created in the outer solder mask layer;

dispensing a layer of optical mask material over the outer solder mask layer and in contact with the sacrificial plugs; and

removing the sacrificial plugs to yield the optical mask layer.

16. The method of claim 15 wherein the optical mask material comprises an epoxy.

17. A method for fabricating an optically-masked microelectronic package, comprising:

producing redistribution layers over the frontside of a semiconductor die, the redistribution layers comprising a body of dielectric material in which interconnect lines are formed; and

applying an optical mask layer over the redistribution layers, the optical mask layer having an opacity greater than the opacity of the body of dielectric material and blocking or obscuring visual observation of an interior portion of the microelectronic package through the redistribution layers, the optical mask layer applied in a solid state as a thin film sheet bonded to an outer surface of the redistribution layers.

18. The method of claim 17 wherein openings are produced in the thin film sheet prior to bonding the thin film sheet to the outer surface of the redistribution layers.

19. The method of claim 17 wherein optical mask layer is composed of a B-stage epoxy, which is partially cured to yield the thin film sheet prior to application over the redistribution layers and which is fully cured when applied over the redistribution layers to bond the thin film sheet to the outer surface thereof.

20. The method of claim 17 wherein the optical mask layer comprises one of the group consisting of an alloy sheet and a film of die attach material adhesively bonded to the outer surface of the redistribution layers.