Through silicon via structure

• US 9,997,497 B2
• Filed: 04/11/2017
• Issued: 06/12/2018
• Est. Priority Date: 06/09/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Jeng, Shin-Puu, Chiou, Wen-Chih, Tsai, Fang Wen, Tsai, Chen-Yu
• Primary Examiner(s): Dang, Phuc
• Application Number:
  US15/485,104
• Publication Number:
  US 20170221861A1
• Time in Patent Office: 427 Days
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0391 Forming a passivation layer after forming the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05548 : Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 : in top view
• CPC Class Codes: H01L 2224/05559 : non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05562 : On the entire exposed surface of the internal layer
• CPC Class Codes: H01L 2224/05568 : the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13023 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13025 : the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1411 : the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/14181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/16113 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]

Abstract

A device includes a through substrate via (TSV) extending through a device substrate. The TSV includes a first conductive material having a sidewall, a protruding end of the TSV protruding from a second side of the device substrate. A liner covers the sidewall of the first conductive material from a below the top surface of the protruding end of the TSV to an opposite end of the TSV. A passivation layer is disposed over the second side of the device substrate and over a portion of the liner disposed on the protruding end of the TSV, the passivation layer having a stair-step surface extending away from the TSV. A conductive interface layer is disposed over the passivation layer, the sidewall of the first conductive material, and the top surface of the protruding end of the TSV. A second conductive material is disposed over the first conductive material.

Claims

1. A device comprising:

a through substrate via extending through a substrate, the substrate comprising a device substrate and metallization layers disposed over a first side of the device substrate, the through substrate via comprising a first conductive material having a sidewall, a protruding end of the through substrate via protruding from a second side of the device substrate, wherein a liner covers the sidewall of the first conductive material from a distance below the top surface of the protruding end of the through substrate via to an end of the through substrate via opposite the protruding end, wherein a portion of the liner protrudes from the second side of the device substrate;

a first passivation layer disposed over the second side of the device substrate and over a portion of the liner that is disposed on the protruding end of the through substrate via, the first passivation layer having a stair-step surface extending away from the through substrate via;

a conductive interface layer disposed over and contacting the first passivation layer, the sidewall of the first conductive material, and the top surface of the protruding end of the through substrate via; and

a second conductive material disposed over the conductive interface layer and the first conductive material.

2. The device of claim 1, further comprising conductive bumps disposed on the metallization layers.

3. The device of claim 1, further comprising a second passivation layer disposed over the second conductive material.

4. The device of claim 3, further comprising forming an opening through the second passivation layer and connecting an external device to the through substrate via through the opening.

5. The device of claim 4, wherein the external device is a semiconductor die.

6. The device of claim 1, wherein the second conductive material is part of a redistribution line.

7. The device of claim 1, further comprising a seed layer disposed over the conductive interface layer.

8. A device comprising:

a liner disposed on sidewalls of an opening that extends through a substrate, the liner protruding from a first side of the substrate;

a first conductive material disposed within the opening and protruding from the first side of the substrate;

a first passivation layer disposed over the first side of the substrate and the first conductive material, the first passivation layer comprising a dielectric material, the first passivation layer having a first portion adjacent to the first side of the substrate and a second portion adjacent to the first conductive material that is protruding from the first side of the substrate, wherein the second portion of the first passivation layer extends farther from the substrate than the first portion of the first passivation layer, and wherein the liner that is protruding from the first side of the substrate extends farther from the substrate than the first portion of the first passivation layer; and

a second conductive material disposed over the first portion of the first passivation layer and disposed over the sidewalls and the top surface of the first conductive material that is protruding from the first side of the substrate.

9. The device of claim 8, further comprising a conductive interface layer disposed between the first conductive material and the second conductive material.

10. The device of claim 8, further comprising a seed layer disposed between the first conductive material and the second conductive material.

11. The device of claim 8, wherein the first passivation layer and the liner both comprise a first material.

12. The device of claim 11, wherein the first material comprises silicon nitride.

13. The device of claim 8, wherein the second conductive material is part of a redistribution line.

14. The device of claim 8, further comprising a second passivation layer at least partially covering a sidewall of the second conductive material.

15. A device comprising:

a first through substrate via extending from a first side of a substrate into the substrate, wherein a liner is interposed between the first through substrate via and the substrate, wherein the first through substrate via extends through at least one metallization layer adjacent the substrate, wherein the first through substrate via and the liner protrude from a second side of the substrate;

a dielectric layer over the through substrate via and the liner, wherein a first portion of the dielectric layer contacting the liner extends farther from the substrate than a second portion of the dielectric layer at a location between the first through substrate via and an adjacent second through substrate via, wherein the liner extends farther from the substrate than the first portion of the dielectric layer; and

a first semiconductor device electrically connecting the first through substrate via and the second through substrate via in a flip-chip configuration.

16. The device of claim 15, wherein the first semiconductor device is a semiconductor die.

17. The device of claim 16, wherein the first through substrate via is electrically connected to a second semiconductor device, wherein the first through substrate via is interposed between the first semiconductor device and the second semiconductor device.

18. The device of claim 17, wherein the second semiconductor device is a printed circuit board.

19. The device of claim 15, further comprising a conductive material in contact with a sidewall of the first through substrate via and a sidewall of the second through substrate via.

20. The device of claim 19, wherein the conductive material is part of a redistribution layer.