Semiconductor package assembly

• US 9,997,498 B2
• Filed: 06/16/2017
• Issued: 06/12/2018
• Est. Priority Date: 03/13/2015
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Lin, Tzu-Hung, Hsiao, Ching-Wen, Peng, I-Hsuan
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US15/624,790
• Publication Number:
  US 20170287877A1
• Time in Patent Office: 361 Days
• Field of Search: 257686, 257698, 257700, 257737, 257738, 257E23123, 257E23169, 257E23174, 361814
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/92133 the second connecting process involving a bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/19011 : including integrated passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor die, a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure, and a passive device, embedded in the redistribution layer (RDL) structure and coupled to the semiconductor die.

Claims

1. A semiconductor package assembly, comprising:

a semiconductor die;

a first molding compound covering a back surface of the semiconductor die;

a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure;

a passive device, embedded in the RDL structure and coupled to the semiconductor die;

conductive structures disposed on a first surface of the RDL structure, the first surface facing away from the semiconductor die, wherein the conductive structures are coupled to the RDL structure, and a thickness of the passive device is less than a diameter of the conductive structures as viewed in vertical cross-section; and

a second molding compound disposed on the front surface of the semiconductor die;

wherein the RDL structure comprises conductive traces extended into the second molding compound.

2. The semiconductor package assembly as claimed in claim 1, wherein the second molding compound is embedded in the RDL structure.

3. The semiconductor package assembly as claimed in claim 2, further comprising:

a conductive bump passing through the second molding compound, wherein the passive device is coupled to the semiconductor die through the conductive bump.

4. The semiconductor package assembly as claimed in claim 2, wherein a sidewall of the second molding compound is surrounded by the RDL structure.

5. The semiconductor package assembly as claimed in claim 2, wherein the first molding compound is separated from the second molding compound through the semiconductor die and the RDL structure.

6. The semiconductor package assembly as claimed in claim 2, wherein an interface between the passive device and the second molding compound is aligned to a first surface of the RDL structure, which is away from the semiconductor die.

7. The semiconductor package assembly as claimed in claim 1, wherein the passive device is coupled to the semiconductor die without using the conductive traces of the RDL structure.

8. A semiconductor package assembly, comprising:

a semiconductor die;

a first molding compound disposed on a first surface of the semiconductor die;

a redistribution layer (RDL) structure disposed on a second surface opposite the first surface of the semiconductor die;

a passive device disposed on a second molding compound and coupled to the semiconductor die, wherein a surface of the passive device is aligned to a first surface of the RDL structure, the first surface of the RDL structure facing away from the semiconductor die; and

conductive structures disposed on the first surface of the RDL structure, wherein the conductive structures are coupled to the RDL structure, and a thickness of the passive device is less than a diameter of the conductive structures as viewed in vertical cross-section.

9. The semiconductor package assembly as claimed in claim 8, wherein the second molding compound is disposed on the second surface of the semiconductor die and embedded in the RDL structure, and wherein the second molding compound is separated from the first molding compound through the RDL structure.

10. The semiconductor package assembly as claimed in claim 9, wherein the RDL structure and the second molding compound cover different portions of the second surface of the semiconductor die.

11. The semiconductor package assembly as claimed in claim 9, further comprising:

a conductive bump passing through the second molding compound, wherein the passive device is coupled to the semiconductor die through the conductive bump.

12. The semiconductor package assembly as claimed in claim 9, wherein a sidewall of the second molding compound is surrounded by the RDL structure.

13. The semiconductor package assembly as claimed in claim 9, wherein the passive device is embedded in the RDL structure.

14. The semiconductor package assembly as claimed in claim 8, further comprising:

conductive structures disposed on the first surface of the RDL structure, wherein the conductive structures are coupled to the RDL structure.

15. The semiconductor package assembly as claimed in claim 8, wherein the RDL structure comprises conductive traces extended into the second molding compound.

16. A semiconductor package assembly, comprising:

a semiconductor die;

a first molding compound in contact with a first surface of the semiconductor die;

a redistribution layer (RDL) structure covering a first portion of a second surface opposite the first surface of the semiconductor die;

a first underfill covering a second portion of the second surface of the semiconductor die and embedded in the RDL structure;

a passive device covering the second portion of the second surface of the semiconductor die, wherein the first underfill is disposed between the semiconductor die and the passive device; and

conductive structures disposed on a first surface of the RDL structure, the first surface of the RDL structure facing away from the semiconductor die, wherein the conductive structures are coupled to the RDL structure, and a thickness of the passive device is less than a diameter of the conductive structures as viewed in vertical cross-section;

wherein the RDL structure comprises conductive traces extended into the first underfill.

17. The semiconductor package assembly as claimed in claim 16, wherein the first underfill is separated from the first molding compound through the RDL structure.

18. The semiconductor package assembly as claimed in claim 16, further comprising:

a conductive bump passing through the first underfill, wherein the passive device is coupled to the semiconductor die through the conductive bump.

19. The semiconductor package assembly as claimed in claim 16, wherein the passive device is embedded in the RDL structure.

20. The semiconductor package assembly as claimed in claim 16, wherein an interface between the passive device and the first underfill is aligned to a first surface of the RDL structure, which is away from the semiconductor die.

21. The semiconductor package assembly as claimed in claim 16, wherein the passive device is coupled to the semiconductor die without using the conductive traces of the RDL structure.